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MPC5645S Datasheet(PDF) 106 Page - Freescale Semiconductor, Inc

Part # MPC5645S
Description  Qorivva MPC5645S Microcontroller Data Sheet
PDF  146 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC5645S Datasheet(HTML) 106 Page - Freescale Semiconductor, Inc

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Qorivva MPC5645S Microcontroller Data Sheet, Rev. 8
106
Freescale Semiconductor
•
PCLK latches data into the panel on its positive edge (when positive polarity is selected). In active
mode, PCLK runs continuously. This signal frequency could be from 5 to 66 MHz depending on
the panel type.
•
HSYNC causes the panel to start a new line. It always encompasses at least one PCLK pulse.
•
VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.
•
DE acts like an output enable signal to the LCD panel. This output enables the data to be shifted
onto the display. When disabled, the data is invalid and the trace is off.
Figure 22. TFT LCD interface timing overview1
4.18.3.1
Interface to TFT LCD Panels—Pixel Level Timings
Figure 23 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and
data. All parameters shown in the diagram are programmable. This timing diagram corresponds to positive
polarity of the PCLK signal (meaning the data and sync signals change on the rising edge) and active-high
polarity of the HSYNC, VSYNC and DE signals. The user can select the polarity of the HSYNC and
VSYNC signals via the SYN_POL register, whether active-high or active-low. The default is active-high.
The DE signal is always active-high.
Pixel clock inversion and a flexible programmable pixel clock delay are also supported. They are
programmed via the DCU Clock Confide Register (DCCR) in the system clock module.
The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register. The PW_H,
BP_H and FP_H parameters are programmed via the HSYN PARA register. The PW_V, BP_V and FP_V
parameters are programmed via the VSYN_PARA register.
1. In Figure 22, the “LD[23:0]” signal is “line data,” an aggregation of the DCU’s RGB signals—R[0:7], G[0:7] and B[0:7].
LINE 1
LINE 2
LINE 3
LINE 4
LINE n-1
LINE n
VSYNC
HSYNC
HSYNC
DE
PCLK
LD[23:0]
2
13
m-1
m



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