MPC5645S datasheet(108/146 Pages) FREESCALE

108 / 146 page

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 8

108

Freescale Semiconductor

Figure 24. Vertical sync pulse

4.18.3.2

Interface to TFT LCD panels—access level

Table 56. LCD Interface Timing Parameters1,2,3,4—Access Level

1 The characteristics in this table are based on the assumption that data is output at +ve edge and displays latch data on -ve

edge.

2 Intra bit skew is less than 2 ns.

3 Load CL = 50 pf for frequency up to 20 MHz.

4 Load CL = 25 pf for display freq from 20 to 32 MHz.

Num

Symbol

Characteristic

Min.

Value

Typical

Value

Max.

Value

Unit

SpecID

1tCKP

CC5

5 Parameter values guaranteed by design.

D PDI Clock Period

31.25

—

A3.12

2tCHD

CC5

D Duty cycle

—

A3.13

3tDSU

CC5

D interface data setup time

—

A3.14

4tDHD

CC5

D PDI interface data access hold time

—

A3.15

5tCSU

CC5

D PDI interface control signal setup time

—

A3.16

6tCHD

CC5

D PDI interface control signal hold time

—

A3.17

7CC5

D TFT interface data valid after pixel clock

—

A3.18

8CC5

D TFT interface HSYNC valid after pixel clock

—

A3.19

9CC5

D TFT interface VSYNC valid after pixel clock

—

5.5

A3.20

CC5

D TFT interface DE valid after pixel clock

—

5.6

A3.21

CC5

D TFT interface hold time for data and control

bits

—

A3.22

CC5

D Relative skew between the data bits

—

3.7

A3.23

Start of Frame

HSYNC

LD[23:0]

HSYNC

tPWV

tBPV

tVSP

tHCP

tFPV

DELTA_Y

Invalid Data

(Line Data)

tSH

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