TFB2022AI

FUTUREBUS+ DATA PATH UNIT

SLLS183 − AUGUST 1994

Copyright

1

POST OFFICE BOX 655303

POST OFFICE BOX 1443

TFB2022A With an Operating Range of

−20

°C to 85°C

Compliant to Futurebus+ Standard

(IEEE Std 896.1−1991)

Microprocessors Such as SPARC

, 680x0,

88xxx, 80x86, and Alpha AXP



TFB2002A Futurebus+ I/O Controller or

Standalone With a User-Defined Controller

Board

Whether Transaction Is to Host Memory,

Extended Unit Space, Message-Passing

Mailbox, or Other CSR Location

Are Provided on Chip

Transfers

Transaction

description

The TFB2022AI data path unit (DPU) is a member of the Texas Instruments Futurebus+ (FB+) chip set. This

chip set provides an integrated approach to the Futurebus+ interface that reduces new-product design time,

allows more functionality per circuit board, improves overall interface reliability, and reduces end-user down time

through built-in test capabilities. The Futurebus+ chip set is capable of supporting 32- or 64-bit data widths in

any combination on both the host-bus interface (HIF) and Futurebus+. The address width is programmable to

be 32 bits or 36 bits (with either data width).

The TFB2022AI may be used with a TFB2002B Futurebus+ I/O controller to provide a complete 64-bit Profile-B

interface. It allows great flexibility in the design of the system and in the host features that may be supported.

It may also be used with a user-defined controller to provide a variety of performance features. When used

together, the TFB2022AI and TFB2002B provide the Futurebus+ and host-bus protocol control for the first

64 bits of data and 36 bits of address. The TFB2022AI contains a bidirectional FIFO for high-speed transmission

of data in either compelled or packet mode, address control for 36 bits of address, and related CSR locations.

All Profile-A- and Profile-B-required CSRs are implemented either on this device or the TFB2002B.

The TFB2022AI is optimized for Profile-B modules. Several processors may reside on a single module with the

DPU as long as they do not require the DPU/IOC to understand cache-coherent operation. The module may

contain memory or I/O units in addition to processors. The TFB2022AI is best suited for I/O or memory modules.

The MS<1:0> signals provide a preaddress decode mechanism, enabling the user to implement simplified

decode logic in the logic interface. These signals indicate whether an access is being made to host memory,

extended units space, host CSR space, or to a message mailbox.

The TFB2022AI is offered in a 240-pin metal quad flat package (MFP). The TFB2022AI is characterized for

operation over the industrial temperature range of − 20

°C to 85°C.

NOTE: To maintain consistency with the notation used in the Futurebus+ standard (IEEE Std 896.1−1991), an active-low signal is denoted herein

by use of the trailing asterisk (*) on the signal name.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

SPARC is a trademark of Sun Microsystems, Inc.

Alpha AXP is a trademark of Digital Equipment Corporation.