TI380PCI

PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

SPWS020 – AUGUST 1995

21

POST OFFICE BOX 1443

COMMAND register—configuration space DWORD address (0x04) (continued)

Bit 04: CONTROL[4] controls memory write-and-invalidate cycles. A value of 1 enables the TI380PCI to

generate memory write-and-invalidate cycles.

Bit 05: CONTROL[5] applies to VGA subsystems and is hardwired to 0.

Bit 06: This bit controls the TI380PCI’s response to parity errors. When this bit is set, the TI380PCI takes its

normal action when a parity error is detected. When this bit is reset, the TI380PCI ignores any parity errors that

it detects and continues normal operation. This bit is set to 0 after reset.

Bit 07: CONTROL[7] is hardwired to a 0 since the TI380PCI does not support address / data stepping.

Bit 08: This bit is an enable bit for the SERR driver. A value of 0 disables the SERR driver and a value of 1

enables it. This bit’s state after RST is 0.

Bit 09: CONTROL[9] is hardwired to a 0 since the TI380PCI does not support fast back-to-back transaction to

different devices.

Bits 10 – 15: Reserved. These reserved bits read as 0.

STATUS register—configuration space DWORD address (0x04)

Fast Back-to-Back Capability

Data Parity Detection

DEVSEL Timing

00 – Fast

01 – Medium

10 – Slow

Signal Target Abort

Receive Target Abort

Receive Master Abort

Signal System Error

Detect Parity Error

Reserved

14

12

0

15

10

9

8

7

6

0

10

13

11

Figure 6. Status Register Layout

The STATUS Register records status information for PCI bus-related events. Reads to this register behave

normally. Writes are slightly different in that bits can be reset, but not set. A bit is reset whenever the register

is written, and the data in the corresponding bit location is a 1.

Bits 0 – 6: Reserved

Bit 7: STATUS[7] is hardwired to a 0 as the TI380PCI does not support fast back-to-back cycles as a slave.

Bit 8: This bit is set when three conditions are met: 1) the PCI device asserted PERR itself or observed PERR

asserted; 2) the device setting the bit acted as the bus master for the operation in which the error occurred; 3) the

parity error response bit (command register) is set.

Bits 9 – 10: DEVSEL timing for the TI380PCI is set to 01 (medium).

Bit 11: This bit is set whenever TI380PCI terminates a transaction with slave-abort.