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RM48L952 Datasheet(PDF) 87 Page - Texas Instruments

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Part # RM48L952
Description  RM48L952 16/32-Bit RISC Flash Microcontroller
PDF  156 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

RM48L952 Datasheet(HTML) 87 Page - Texas Instruments

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RM48L952
www.ti.com
SPNS177
– SEPTEMBER 2011
Table 4-28. EMIF Asynchronous Memory Switching Characteristics(1)(2)(3)
NO
Parameter
Value
Unit
MIN
NOM
MAX
Reads and Writes
1
td(TURNAROUND)
Turn around time
(TA)*E -3
(TA)*E
(TA)*E + 3
ns
Reads
3
tc(EMRCYCLE)
EMIF read cycle time (EW = 0)
(RS+RST+RH)*
(RS+RST+RH)*
(RS+RST+RH)*
ns
E -3
E
E + 3
EMIF read cycle time (EW = 1)
(RS+RST+RH+( (RS+RST+RH+( (RS+RST+RH+(
ns
EWC*16))*E -3
EWC*16))*E
EWC*16))*E +
3
4
tsu(EMCEL-EMOEL)
Output setup time,
(RS)*E-3
(RS)*E
(RS)*E+3
ns
EMIFnCS[4:2] low to EMIFnOE
low (SS = 0)
Output setup time,
-3
0
+3
ns
EMIFnCS[4:2] low to EMIFnOE
low (SS = 1)
5
th(EMOEH-EMCEH)
Output hold time, EMIFnOE high
(RH)*E -3
(RH)*E
(RH)*E + 3
ns
to EMIFnCS[4:2] high (SS = 0)
Output hold time, EMIFnOE high
-3
0
+3
ns
to EMIFnCS[4:2] high (SS = 1)
6
tsu(EMBAV-EMOEL)
Output setup time, EMIFBA[1:0]
(RS)*E-3
(RS)*E
(RS)*E+3
ns
valid to EMIFnOE low
7
th(EMOEH-EMBAIV)
Output hold time, EMIFnOE high
(RH)*E-3
(RH)*E
(RH)*E+3
ns
to EMIFBA[1:0] invalid
8
tsu(EMBAV-EMOEL)
Output setup time,
(RS)*E-3
(RS)*E
(RS)*E+3
ns
EMIFADDR[21:0] valid to
EMIFnOE low
9
th(EMOEH-EMAIV)
Output hold time, EMIFnOE high
(RH)*E-3
(RH)*E
(RH)*E+3
ns
to EMIFADDR[21:0] invalid
10
tw(EMOEL)
EMIFnOE active low width (EW
(RST)*E-3
(RST)*E
(RST)*E+3
ns
= 0)
EMIFnOE active low width (EW
(RST+(EWC*16
(RST+(EWC*16
(RST+(EWC*16
ns
= 1)
)) *E-3
))*E
)) *E+3
11
td(EMWAITH-EMOEH)
Delay time from EMIFnWAIT
3E-3
4E
4E+3
ns
deasserted to EMIFnOE high
Writes
15
tc(EMWCYCLE)
EMIF write cycle time (EW = 0)
(WS+WST+WH
(WS+WST+WH
(WS+WST+WH
ns
)* E-3
)*E
)* E+3
EMIF write cycle time (EW = 1)
(WS+WST+WH
(WS+WST+WH
(WS+WST+WH
ns
+( EWC*16))*E
+(E WC*16))*E
+( EWC*16))*E
-3
+ 3
16
tsu(EMCEL-EMWEL)
Output setup time,
(WS)*E -3
(WS)*E
(WS)*E + 3
ns
EMIFnCS[4:2] low to EMIFnWE
low (SS = 0)
Output setup time,
-3
0
+3
ns
EMIFnCS[4:2] low to EMIFnWE
low (SS = 1)
17
th(EMWEH-EMCEH)
Output hold time, EMIFnWE
(WH)*E-3
(WH)*E
(WH)*E+3
ns
high to EMIFnCS[4:2] high (SS =
0)
(1)
TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle
Configuration Registers. These support the following ranges of values: TA[4
–1], RS[16–1], RST[64–1], RH[8–1], WS[16–1], WST[64–1],
WH[8
–1], and MEWC[1–256]. See the EMIF User’s guide for more information.
(2)
E = EMIF_CLK period in ns.
(3)
EWC = external wait cycles determined by EMIFnWAIT input signal. EWC supports the following range of values. EWC[256
–1]. Note
that the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See
the EMIF User
’s Guide for more information.
Copyright
© 2011, Texas Instruments Incorporated
System Information and Electrical Specifications
87
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