SMJ320C50/SMQ320C50

DIGITAL SIGNAL PROCESSOR

SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001

2

POST OFFICE BOX 1443

description

The SMJ320C50 digital signal processor (DSP) is a high-performance, 16-bit, fixed-point processor

manufactured in 0.72-μm double-level metal CMOS technology. The SMJ320C50 is the first DSP from TI

designed as a fully static device. Full-static CMOS design contributes to low power consumption while

maintaining high performance, making it ideal for applications such as battery-operated communications

systems, satellite systems, and advanced control algorithms.

A number of enhancements to the basic SMJ320C2x architecture give the C50 a minimum 2× performance over

the previous generation. A four-deep instruction pipeline, that incorporates delayed branching, delayed call to

subroutine, and delayed return from subroutine, allows the C50 to perform instructions in fewer cycles. The

addition of a parallel logic unit (PLU) gives the C50 a method for manipulating bits in data memory without using

the accumulator and ALU. The C50 has additional shifting and scaling capability for proper alignment of

multiplicands or storage of values to data memory.

The C50 achieves its low-power consumption through the IDLE2 instruction. IDLE2 removes the functional

clock from the internal hardware of the C50, which puts it into a total-sleep mode that uses only 7 μA. A low-logic

level on an external interrupt with a duration of at least five clock cycles ends the IDLE2 mode.

The C50 is available with two clock speeds. The clock frequencies are 50 MHz, providing a 40-ns cycle time,

and 66 MHz, providing a 30-ns cycle time. The available options are listed in Table 1.

Table 1. Available Options

PART NUMBER

SPEED

SUPPLY

VOLTAGE

TOLERANCE

PACKAGE

SMJ320C50GFAM66

30-ns cycle time

±5%

Pin grid array

SMJ320C50HFGM66

30-ns cycle time

±5%

Quad flat package

SMJ320C50GFAM50

40 ns cycle time

±5%

Pin grid array

SMJ320C50HFGM50

40 ns cycle time

±5%

Quad flat package

30 ns cycle time

±5%

Plastic Quad flat package