SMJ320C50/SMQ320C50

DIGITAL SIGNAL PROCESSOR

SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001

13

POST OFFICE BOX 1443

external divide-by-two clock option

An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left

unconnected, CLKMD1 set high, and CLKMD2 set high. The external frequency is divided by two to generate

the internal machine cycle. The external frequency injected must conform to specifications listed in the timing

requirements table.

PARAMETER

’320C50-50

’320C50-66

UNIT

PARAMETER

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

Cycle time, CLKOUT1

40

†

30

†

ns

Delay time, X2/CLKIN high to CLKOUT1 high/low

3

11

20

3

11

20

ns

Fall time, CLKOUT1

5

5

ns

Rise time, CLKOUT1

5

5

ns

Pulse duration, CLKOUT1 low

H-- 3

H

H+2

H-- 3

H

H+2

ns

Pulse duration, CLKOUT1 high

H-- 3

H

H+2

H-- 3

H

H+2

ns

approaching 0 Hz, but is tested at a minimum of 6.7 MHz to meet device test time requirements.

timing requirements

’320C50-50

’320C50-66

UNIT

MIN

MAX

MIN

MAX

UNIT

Cycle time, X2/CLKIN

20

†

15

†

ns

Fall time, X2/CLKIN

5*

5*

ns

Rise time, X2/CLKIN

5*

5*

ns

Pulse duration, X2/CLKIN low

8

†

7

†

ns

Pulse duration, X2/CLKIN high

8

†

7

†

ns

approaching 0 Hz, but is tested at a minimum of 6.7 MHz to meet device test time requirements.

CLKOUT1

CLKIN

Figure 5. External Divide-by-Two Clock Timing