SM320C50 datasheet(21/37 Pages) TI1

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SMJ320C50/SMQ320C50

DIGITAL SIGNAL PROCESSOR

SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251--1443

EXTERNAL DMA TIMING

switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Note 3)

PARAMETER

MIN

MAX

UNIT

td(HOL-HAL)

Delay time, HOLD low to HOLDA low

†

td(HOH-HAH)

Delay time, HOLD high before HOLDA high

tdis(AZ-HAL)

Disable time, address in the high-impedance state before HOLDA low

H--15‡*

ten(HAH-Ad)

Enable time, HOLDA high to address driven

H--5*

td(XBL-IQL)

Delay time, XBR low to IAQ low

4H*

6H*

td(XBH-IQH)

Delay time, XBR high to IAQ high

2H*

4H*

td(XSL-RDV)

Delay time, read data valid after XSTRB low

th(XSH-RD)

Hold time, read data after XSTRB high

ten(IQL-RDd)

Enable time, IAQ low to read data driven

0*§

2H*

tdis(W)

Disable time, XR/W low to data in the high-impedance state

15*

tdis(I-D)

Disable time, IAQ high to data in the high-impedance state

ten(D-XRH)

Enable time, data from XR/W going high

† HOLD is not acknowledged until current external access request is complete.

‡ This parameter includes all memory control lines.

§ This parameter refers to the delay between the time the condition (IAQ = 0 and XR/W = 1) is satisfied and the time that the SMJ320C50x data

lines become valid.

* This parameter is not production tested.

NOTE 3: X preceding a name refers to the external drive of the signal.

timing requirements

MIN

MAX

UNIT

td(HAL-XBL)

Delay time, HOLDA low to XBR low

0¶

td(IQL-XSL)

Delay time, IAQ low to XSTRB low

0¶

tsu(AV-XSL)

Setup time, Xaddress valid before XSTRB low

tsu(DV-XSL)

Setup time, Xdata valid before XSTRB low

th(XSL-D)

Hold time, Xdata hold after XSTRB low

th(XSL-WA)

Hold time, write Xaddress hold after XSTRB low

tw(XSL)

Pulse duration, XSTRB low

tw(XSH)

Pulse duration, XSTRB high

tsu(RW-XSL)

Setup time, R/W valid before XSTRB low

th(XSH-RA)

Hold time, read Xaddress after XSTRB high

¶ XBR,XR/W, and XSTRB lines should be pulled up with a 10-kΩ resistor to assure that they are in an inactive (high) state during the transition

period between the SMJ320C50x driving them and the external circuit driving them.

NOTE 3. X preceding a name refers to the external drive of the signal.

SM320C50 Datasheet(PDF) 21 Page - Texas Instruments

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