VSENSE

COMP

VOUT

R1

R3

C1

C2

R2

Coea

Roea

gm

1300 mA/V

0.6 V

Power Stage

PH

CO

b

a

c

21 A/V

TPS54821

www.ti.com

SLVSB14

– OCTOBER 2011

The low-side MOSFET may also sink current from the load. If the low-side sinking current limit is exceeded the

low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are

off until the start of the next cycle.

Furthermore, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than

the hiccup wait time which is programmed for 512 switching cycles, the device will shut down itself and restart

after the hiccup time of 16384 cycles. The hiccup mode helps to reduce the device power dissipation under

severe overcurrent conditions.

Thermal Shutdown

The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds

175

°C typically. Once the junction temperature drops below 165°C typically, the internal thermal hiccup timer will

start to count. The device reinitiates the power up sequence after the built-in thermal shutdown hiccup time

(16384 cycles) is over.

Small Signal Model for Loop Response

Figure 25 shows an equivalent model for the device control loop which can be modeled in a circuit simulation

program to check frequency response and transient responses. The error amplifier is a transconductance

amplifier with a gm of 1300

μA/V. The error amplifier can be modeled using an ideal voltage controlled current

source. The resistor Roea (3.07 M

Ω) and capacitor Coea (20.7 pF) model the open loop gain and frequency

response of the error amplifier. The 1-mV ac voltage source between the nodes a and b effectively breaks the

control loop for the frequency response measurements. Plotting a/c and c/b show the small signal responses of

the power stage and frequency compensation respectively. Plotting a/b shows the small signal response of the

appropriate load step amplitude and step rate in a time domain analysis.

Figure 25. Small Signal Model for Loop Response

Simple Small Signal Model for Peak Current Mode Control

Figure 26 is a simple small signal model that can be used to understand how to design the frequency

compensation. The device power stage can be approximated to a voltage controlled current source (duty cycle

modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is

shown in Equation 10 and consists of a dc gain, one dominant pole and one ESR zero. The quotient of the

change in switch current and the change in COMP pin voltage (node c in Figure 25) is the power stage

gain decreases. This variation with load may seem problematic at first glance, but fortunately the dominant pole

moves with load current (see Equation 12). The combined effect is highlighted by the dashed line in Figure 27.

As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover

frequency the same for the varying load conditions which makes it easier to design the frequency compensation.

Copyright

© 2011, Texas Instruments Incorporated

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