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MFRC63002R Datasheet(PDF) 88 Page - NXP Semiconductors |
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MFRC63002R Datasheet(HTML) 88 Page - NXP Semiconductors |
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88 / 118 page ![]() MFRC630 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 6 September 2012 227531 88 of 118 NXP Semiconductors MFRC630 Contactless reader IC 9.12.3 RxWait Selects internal receiver settings. 9.12.4 RxThreshold Selects minimum threshold level for the bit decoder. 5 to 4 RFU - 3 EMD_Sup Enables the EMD suppression according ISO/IEC14443. If an error occurs within the first three bytes, these three bytes are assumed to be EMD, ignored and the FIFO is reset. A collision is treated as an error as well If a valid SOF was received, the EMD_Sup is set and a frame of less than 3 bytes had been received. RX_IRq is not set in this EMD error cases. If RxForceCRCWrite is set, the FIFO should not be read out before three bytes are written into. 2 to 0 Baudrate Defines the baud rate of the receiving signal. 4h: 106 kBd 5h: 212 kBd 6h: 424 kBd 7h: 847 kBd all remaining values are RFU Table 148. RxCtrl bits Bit Symbol Description Table 149. RxWait register (address 36h) Bit 7 6 5 4 3 2 1 0 Symbol RxWaitEtu RxWait Access rights r/w r/w Table 150. RxWait bits Bit Symbol Description 7 RXWaitEtu If set to 0, the RxWait time is RxWait 16/13.56 MHz. If set to 1, the RxWait time is RxWait (0.5/DBFreq). 6 to 0 RxWait Defines the time after sending, where every input is ignored. Table 151. RxThreshold register (address 37h) Bit 7 6 5 4 3 2 1 0 Symbol MinLevel MinLevelP Access rights r/w r/w Table 152. RxThreshold bits Bit Symbol Description 7 to 4 MinLevel Defines the MinLevel of the reception. Note: The MinLevel should be higher than the noise level in the system. 3 to 0 MinLevelP Defines the MinLevel of the phase shift detector unit. |
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