SST48CF024 datasheet(32/60 Pages) SST

32 / 60 page

Data Sheet

CompactFlash Card

SST48CF008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 / 256

S71125-03-000

9/01

375

3.1.3 Memory Mapped Addressing

When the CompactFlash card registers are accessed via memory references, the registers appear in the common

memory space window: 0-2 KByte as follows:

TABLE

3-4: MEMORY MAPPED DECODING

-REG

A10

A9-A4

Offset

-OE=0

-WE=0

Notes

Even RD Data

Even WR Data

1,2

1. Register 0 is accessed with -CE1 low and -CE2 low as a word register on the combined Odd Data Bus and Even Data Bus (D15-D0).

This register may also be accessed by a pair of byte accesses to the offset 0 with -CE1 low and -CE2 high. Note that the address

space of this word register overlaps the address space of the Error and Feature byte-wide registers that lie at offset 1. When

accessed twice as byte register with -CE1 low, the first byte to be accessed is the Even Byte of the word and the second byte

accessed is the Odd Byte of the equivalent word access.

A byte access to address 0 with -CE1 high and -CE2 low accesses the error (read) or feature (write) register.

2. Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1.

Register 8 is equivalent to register 0, while register 9 accesses the Odd Byte. Therefore, if the registers are byte accessed in the

order 9 then 8 the data will be transferred Odd Byte then Even Byte.

Repeated byte accesses to register 8 or 0 will access consecutive (Even then Odd) Bytes from the data buffer. Repeated word

accesses to register 8, 9 or 0 will access consecutive words from the data buffer. Repeated byte accesses to register 9 are not sup-

ported. However, repeated alternating byte accesses to registers 8 then 9 will access consecutive (Even then Odd) Bytes from the

data buffer. Byte accesses to register 9 access only the Odd Byte of the data.

Error

Features

1,2

Sector Count

Sector No.

Cylinder Low

Cylinder High

Select Card/Head

Status

Command

Dup. Even RD Data

Dup. Even WR Data

Dup. Odd RD Data

Dup. Odd WR Data

Dup. Error

Dup. Features

Alt Status

Device Ctl

Drive Address

Reserved

Even RD Data

Even WR Data

3. Accesses to even addresses between 400H and 7FFH access register 8. Accesses to odd addresses between 400H and 7FFH

access register 9. This 1 KByte memory window to the data register is provided so that hosts can perform memory to memory block

moves to the data register when the register lies in memory space.

Some hosts, such as the X86 processors, must increment both the source and destination addresses when executing the memory to

memory block move instruction. Some PCMCIA socket adapters also have auto incrementing address logic embedded within them.

This address window allows these hosts and adapters to function efficiently.

Note that this entire window accesses the Data Register FIFO and does not allow random access to the data buffer within the Com-

pactFlash card.

A word access to address at offset 8 will provide even data on the low-order byte of the data bus, along with odd data at offset 9 on

the high-order byte of the data bus.

Odd RD Data

Odd WR Data

T3-4.0 375

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