2

C

M

ps

fc Vo Co

R

g

Vref gm

p ×

×

×

=

×

×

2

C

M

ps

fc Co

R

g

gm

p ×

×

=

×

L

c

c

R

Co

C

R

×

=

L

c

c

R

Co

C

R

×

=

1

2

O

L

fp

C

R

p

=

×

×

Re

Roll

C

sr Co

C

R

×

=

Re

Roll

C

sr Co

C

R

×

=

1

2

Roll

C

Roll

fp

R

C

p

=

×

×

×

1

1

2

ff

ff

C

fz

R

p

=

×

×

×

TPS65252

SLVSAM1B

– DECEMBER 2010 – REVISED FEBRUARY 2011

www.ti.com

To calculate the external compensation components follow the following steps:

TYPE II CIRCUIT

TYPE III CIRCUIT

Select switching frequency that is appropriate for

application depending on L, C sizes, output ripple, EMI

concerns and etc. Switching frequencies between 500 kHz

Use type III circuit for switching

and 1 MHz give best trade off between performance and

frequencies higher than 500 kHz.

cost. When using smaller L and Cs, switching frequency

can be increased. To optimize efficiency, switching

frequency can be lowered.

Select cross over frequency (fc) to be less than 1/5 to 1/10

Suggested

Suggested

of switching frequency.

fc = fs/10

fc = fs/10

the converter dominant pole

impedance COMP node. Make sure that

is at least twice the cross over frequency.

the phase margin at the crossover frequency. Make sure

NA

Slope Compensation

The device has a built-in slope compensation ramp. The slope compensation can prevent sub harmonic

oscillations in peak current mode control.

Input Capacitor

Use 10-

µF X7R/X5R ceramic capacitors at the input of the converter inputs. These capacitors should be

connected as close as physically possible to the input pins of the converters.

Bootstrap Capacitor

The device has two integrated boot regulators and requires a small ceramic capacitor between the BST and LX

pin to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be

0.047

µF. A ceramic capacitor with an X7R or X5R grade dielectric is recommended because of the stable

characteristics over temperature and voltage.

Power Good

The PGOOD pin is an open drain output. The PGOOD pin is pulled low when any buck converter is pulled below

85% of the nominal output voltage. The PGOOD is pulled up when both buck converters

’ outputs are more than

90% of its nominal output voltage. The default reset time is 256 ms. The polarity of the PGOOD is active high.

16

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