49LF002 datasheet(4/36 Pages) SST

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Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

S71161-06-000

9/01

504

FIGURE 2: WRITE WAVEFORMS

TABLE

2: FWH WRITE CYCLE

Clock

Cycle

Field

Name

Field Contents

FWH[3:0]1

FWH[3:0]

Direction

Comments

START

1110

FWH4 must be active (low) for the part to respond.

Only the last start field (before FWH4 transitioning

high) should be recognized. The START field contents

indicate a FWH memory read cycle.

IDSEL

0000 to 1111

Indicates which SST49LF00xA device should

respond. If the IDSEL (ID select) field matches the

value ID[3:0], then that particular device will respond

to the whole bus cycle.

3-9

IMADDR

YYYY

These seven clock cycles make up the 28-bit memory

address. YYYY is one nibble of the entire address.

Addresses are transferred most-significant nibble first.

IMSIZE

0000 (1 byte)

This size field indicates how many bytes will be

transferred during multi-byte operations. The FWH

only supports single-byte writes. IMSIZE=0000b

DATA

YYYY

This field is the least-significant nibble of the data byte.

This data is either the data to be programmed into the

flash memory or any valid flash command.

DATA

YYYY

This field is the most-significant nibble of the data byte.

TAR0

1111

IN then Float

In this clock cycle, the master (Intel ICH) has driven the

then float bus to all ‘1’s and then floats the bus prior to

the next clock cycle. This is the first part of the bus

“turnaround cycle.”

TAR1

1111 (float)

Float then OUT

The SST49LF00xA takes control of the bus during this

cycle. During the next clock cycle it will be driving the

“sync” data.

RSYNC

0000

OUT

The SST49LF00xA outputs the values 0000, indicat-

ing that it has received data or a flash command.

TAR0

1111

OUT then Float

In this clock cycle, the SST49LF00xA has driven the

bus to all then float ‘1’s and then floats the bus prior to

the next clock cycle. This is the first part of the bus

“turnaround cycle.”

TAR1

1111 (float)

Float then IN

The master (Intel ICH) resumes control of the bus during

this cycle.

T2.4 504

1. Field contents are valid on the rising edge of the present clock cycle.

CLK

FWH4

FWH[3:0]

504 ILL F60.1

STR

DATA

TAR

RSYNC

IMS

IMADDR

IDS

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