Communication Interfaces

• Up to 100 kbps with maximum bus loading

• Multi-master operation

• Software programmable for one of 64 different serial clock frequencies

• Programmable slave address and glitch input filter

• Interrupt or DMA driven byte-by-byte data transfer

• Arbitration lost interrupt with automatic mode switching from master to slave

• Calling address identification interrupt

• Bus busy detection broadcast and 10-bit address extension

• Address matching causes wake-up when processor is in low power mode

4.5.6.2 UART1 to UARTx

• Full-duplex, standard non-return-to-zero (NRZ) format

• Double-buffered transmitter and receiver with separate enables

• Programmable baud rates (13-bit modulo divider)

• Interrupt-driven or polled operation:

• Transmit data register empty and transmission complete

• Receive data register full

• Receive overrun, parity error, framing error, and noise error

• Idle receiver detect

• Active edge on receive pin

• Break detect supporting LIN

• Hardware parity generation and checking

• Programmable 8-bit or 9-bit character length

• Programmable 1-bit or 2-bit stop bits

• Receiver wakeup by idle-line or address-mark

• Optional 13-bit break character generation / 11-bit break character detection

• Selectable transmitter output polarity

4.5.6.3 UART0

• Full-duplex operation

• Standard mark/space non-return-to-zero (NRZ) format

• 13-bit baud rate selection with fractional divide of 32

• Programmable 8-bit or 9-bit data format

• Separately enabled transmitter and receiver

• Programmable transmitter output polarity

• Programmable receive input polarity

• 13-bit break character option

• 11-bit break character detection option

• Two receiver wakeup methods:

• Idle line wakeup

• Address mark wakeup

• Address match feature in receiver to reduce address mark wakeup ISR overhead

• Interrupt or DMA driven operation

• Receiver framing error detection

• Hardware parity generation and checking

4.5.6

Communication Interfaces

KL14/KL15 Product Brief, Rev. 2, 6/2012

16

Preliminary

Freescale Semiconductor, Inc.

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