• Configurable oversampling ratio to support from 1/4 to 1/32 bit-time noise detection

• Operation in low power modes

4.5.6.4 Serial Peripheral Interface (SPI)

• Master and slave mode

• Full-duplex, three-wire synchronous transfers

• Programmable transmit bit rate

• Double-buffered transmit and receive data registers

• Serial clock phase and polarity options

• Slave select output

• Mode fault error flag with CPU interrupt capability

• Control of SPI operation during wait mode

• Selectable MSB-first or LSB-first shifting

• Support for both transmit and receive by DMA

Human Machine Interface

4.5.7.1 General Purpose Input/Output (GPIO)

• Hysteresis and configurable pull up device on all input pins

• Configurable drive strength on some output pins

• Independent pin value register to read logic level on digital pin

4.5.7.2 Touch Sensor Input (TSI)

• Support up to 16 external electrodes

• Automatic detection of electrode capacitance across all operational power modes

• Internal reference oscillator for high-accuracy measurement

• Configurable software or hardware scan trigger

• Fully support Freescale touch sensing software (TSS) library

• Capability to wake MCU from low power modes

• Compensate for temperature and supply voltage variations

• High sensitivity change with 16-bit resolution register

• Configurable up to 4096 scan times.

• Support DMA data transfer

5 Power modes

The power management controller (PMC) provides multiple power options to allow the user to optimize power consumption

for the level of functionality needed.

Depending on the stop requirements of the user application, a variety of stop modes are available that provide state retention,

partial power down or full power down of certain logic and/or memory. I/O states are held in all modes of operation. The

following table compares the various power modes available.

For each run mode there is a corresponding wait and stop mode. Wait modes are similar to ARM sleep modes. Stop modes

(VLPS, STOP) are similar to ARM sleep deep mode. The very low power run (VLPR) operating mode can drastically reduce

runtime power when the maximum bus frequency is not required to handle the application needs.

4.5.7

Human Machine Interface

KL14/KL15 Product Brief, Rev. 2, 6/2012

Freescale Semiconductor, Inc.

Preliminary

17

General Business Information