Table 5. Chip power modes (continued)

Chip mode

Description

Core mode

Normal

recovery

method

VLLS0 (Very

Low Leakage

Stop 0)

Most peripherals are disabled (with clocks stopped), but LLWU,

LPTMR, RTC, TSI can be used. NVIC is disabled; LLWU is used to

wake up.

All of SRAM_U and SRAM_L are powered off.

LPO shut down, optional POR brown-out detection

Sleep Deep

Wakeup Reset2

1. Resumes normal run mode operation by executing the LLWU interrupt service routine.

2. Follows the reset flow with the LLWU interrupt flag set for the NVIC.

6 Revision History

The following table provides a revision history for this document.

Table 6. Revision history

Rev. No.

Date

Substantial Changes

1

3/16/2012

Initial publish

2

6/4/2012

Updated Kinetis KL series of MCU portfolio diagram.

Updated Memory and package options section.

Revision History

KL14/KL15 Product Brief, Rev. 2, 6/2012

Freescale Semiconductor, Inc.

Preliminary

19

General Business Information