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TM4EP72CJB Datasheet(PDF) 8 Page - Texas Instruments

Part # TM4EP72CJB
Description  EXTENDED-DATA-OUT BUFFERED DYNAMIC RAM MODULES
PDF  13 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TM4EP72CJB Datasheet(HTML) 8 Page - Texas Instruments

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TM4EP72BPB, TM4EP72BJB, 4194304 BY 72BIT
TM4EP72CPB, TM4EP72CJB 4194304 BY 72BIT
EXTENDEDDATAOUT BUFFERED DYNAMIC RAM MODULES
SMMS686A − AUGUST 1997 − REVISED FEBRUARY 1998
8
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
capacitance
over recommended ranges of supply voltage and ambient temperature,
f = 1 MHz (see Note 2)
PARAMETER
’4EP72xxB
UNIT
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, A0 − A10
6
pF
Ci(OE)
Input capacitance, OEx
6
pF
Ci(CAS)
Input capacitance, CASx
6
pF
Ci(RAS)
Input capacitance, RASx
65
pF
Ci(W)
Input capacitance, WEx
6
pF
Co
Output capacitance
9
pF
NOTE 2: VDD= NOM supply voltage ± 10%, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and ambient temperature
(see Note 3)
PARAMETER
’4EP72xxB-50
’4EP72xxB-60
’4EP72xxB-70
UNIT
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
tAA
Access time from column address (see Note 4)
30
35
40
ns
tCAC
Access time from CASx (see Note 4)
18
20
23
ns
tCPA
Access time from CASx precharge (see Note 4)
33
40
45
ns
tRAC
Access time from RASx (see Note 4)
50
60
70
ns
tOEA
Access time from OEx (see Note 4)
18
20
23
ns
tCLZ
Delay time, CASx to output in low impedance
2
2
2
ns
tREZ
Output buffer turn off delay from RASx (see Note 5)
3
13
3
15
3
18
ns
tCEZ
Output buffer turn off delay from CASx (see Note 5)
5
18
5
20
5
23
ns
tOEZ
Output buffer turn off delay from OEx (see Note 5)
5
18
5
20
5
23
ns
tWEZ
Output buffer turn off delay from WEx (see Note 5)
3
13
3
15
3
18
ns
NOTES:
3. With ac parameters, it is assumed that tT = 2 ns.
4. Access times are measured with output reference levels of VOH = 2 V and VOL = 0.8 V.
5. The maximum values of tREZ, tCEZ, tOEZ, and tWEZ are specified when the outputs are no longer driven. Data in must not be driven
until one of the applicable maximum values is satisfied.
EDO timing requirements (see Note 3)
’4EP72xxB-50
’4EP72xxB-60
’4EP72xxB-70
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
tHPC
Cycle time, EDO page mode, read-write
20
25
30
ns
tPRWC Cycle time, EDO read-write
55
64
71
ns
tCSH
Delay time, RASx active to CASx precharge
38
46
56
ns
tCHO
Hold time, OEx from CASx
7
10
10
ns
tDOH
Hold time, output from CASx
5
5
5
ns
tCAS
Pulse duration, CASx active
8
10 000
10
10 000
12
10 000
ns
tWPE
Pulse duration, WEx active (output disable only)
7
7
7
ns
tOCH
Setup time, OEx before CASx
8
10
10
ns
tCP
Pulse duration, CASx precharge
8
10
10
ns
tOEP
Precharge time, OEx
5
5
5
ns
NOTE 3: With ac parameters, it is assumed that tT = 2 ns.



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