TM4EP72BPB, TM4EP72BJB, 4194304 BY 72BIT

TM4EP72CPB, TM4EP72CJB 4194304 BY 72BIT

EXTENDEDDATAOUT BUFFERED DYNAMIC RAM MODULES

SMMS686A − AUGUST 1997 − REVISED FEBRUARY 1998

10

POST OFFICE BOX 1443

ac timing requirements (see Note 3) (continued)

’4EP72xxB-50

’4EP72xxB-60

’4EP72xxB-70

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

tRCD

Delay time, RASx to CASx ( see Note 9)

10

32

12

40

12

47

ns

tRPC

Delay time, RASx precharge to CASx

3

3

3

ns

tRSH

Delay time, CASx active to RASx precharge

18

20

23

ns

tRWD

Delay time, RASx to write command (read-write only)

67

79

92

ns

tTAA

Access time from address (test mode)

30

35

40

ns

tTCPA

Access time from column precharge (test mode)

40

45

50

ns

tTRAC

Access time from RASx (test mode)

50

60

70

ns

tREF

Refresh time interval

32

32

32

ms

tT

Transition time

2

30

2

30

2

30

ns

NOTES:

3. With ac parameters, it is assumed that tT = 2 ns.

9. The maximum value is specified only to ensure access time.