CYRF69313 datasheet(39/80 Pages) CYPRESS

39 / 80 page

CYRF69313

Document Number: 001-66503 Rev. *C

Page 39 of 80

Table 50. P0.3/INT1–P0.4/INT2 Configuration (P03CR–P04CR) [0x08–0x09] [R/W]

Bit #

Field

Reserved

Int Act Low

TTL Thresh

Reserved

Open Drain

Pull-up

Enable

Output

Enable

Read/Write

–

R/W

–R/W

R/W

Default

These registers control the operation of pins P0.3–P0.4, respectively. These pins are shared between the P0.3–P0.4 GPIOs and

the INT0–INT2. These registers exist in all CYRF69313 parts. The INT0–INT2 interrupts are different than all the other GPIO

interrupts. These pins are connected directly to the interrupt controller to provide three edge-sensitive interrupts with

independent interrupt vectors. These interrupts occur on a rising edge when Int act Low is clear and on a falling edge when Int

act Low is set. These pins are enabled as interrupt sources in the interrupt controller registers (Table 76 on page 54 and Table

74 on page 52)

To use these pins as interrupt inputs configure them as inputs by clearing the corresponding Output Enable. If the INT0–INT2 pins

are configured as outputs with interrupts enabled, firmware can generate an interrupt by writing the appropriate value to the P0.3

and P0.4 data bits in the P0 Data Register

Regardless of whether the pins are used as Interrupt or GPIO pins the Int Enable, Int act Low, TTL Threshold, Open Drain, and

Pull-up Enable bits control the behavior of the pin

The P0.3/INT1–P0.4/INT2 pins are individually configured with the P03CR (0x08), and P04CR (0x09), respectively.

Note Changing the state of the Int Act Low bit can cause an unintentional interrupt to be generated. When configuring these

interrupt sources, it is best to follow the following procedure:

1. Disable interrupt source

2. Configure interrupt source

3. Clear any pending interrupts from the source

4. Enable interrupt source

Table 51. P0.7 Configuration (P07CR) [0x0C] [R/W]

Bit #

Field

Reserved

Int Enable

Int Act Low

TTL Thresh

Reserved

Open Drain

Pull-up

Enable

Output

Enable

Read/Write

–

R/W

–

R/W

Default

This register controls the operation of pin P0.7.

Table 52. P1.0/D+ Configuration (P10CR) [0x0D] [R/W]

Bit #

Field

Reserved

Int Enable

Int Act Low

Reserved

5 K pull-up

enable

Output

Enable

Read/Write

R/W

–

––

–

R/W

Default

This register controls the operation of the P1.0 (D+) pin when the USB interface is not enabled, allowing the pin to be used as a

GPIO pin which is pulled up. See Table 79 on page 56 for information on enabling USB. When USB is enabled, none of the

controls in this register have any effect on the P1.0 pin

Note The P1.0 is an open drain only output. It can actively drive a signal low, but cannot actively drive a signal high

Bit 1

5 K Pull-up Enable

0 = Disable the 5 k

 pull-up resistors

1 = Enable 5 k

 pull-up resistors for both P1.0 and P1.1. Enable the use of the P1.0 (D+) and P1.1 (D–) pins as pulled up GPIOs

Bit 0

This bit enables the output on P1.0/D+. This bit should be cleared in sleep mode.

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