– 13 –

CXA2647N

• Center Error

The signals input to the A and D pins and the B and C pins are arithmetically amplified and the center error

signal is output.

ROM/RW switching and offset addition functions are incorporated.

VC

RW

48k

12k

30k

ROM

A

DVC

VOFST

124

124

6

CEI 21

CE

20

30k

D 9

30k

B

30k

24k

96k

24k

50k

200k

96k

7

C

ROM

RW

ROM

RW

8

CE = Gain {(B + C) – (A + D)} signal is arithmetically amplified.

Low frequency gain

ROM: 15.5dB

RW: 27.5dB

Cut-off frequency fc (typ.)

ROM: 200kHz

RW:

200kHz

• Output DC Level Shift

The FE, TE and CE output DC voltages are level shifted to the digital VC voltage (DVC).

The reference voltage of this IC is the VC voltage, and only the output reference voltage changes.

order to protect the DSP IC.

DVC

VOFST

30k

30k

VC

15k

The VC and DVC voltages are arithmetically amplified

and output as the VOFST voltage.

The VOFST voltage serves as the level shift reference

voltage, and is distributed to each block.

VOFST = 2VC –DVC

• SW

This controls the laser (APC) on/off, active/sleep mode, and ROM/RW mode switching.

Switching is controlled by the voltage applied to the SW pin.

12

SW

SW

ROM/RW

Active/Sleep

APC ON/OFF

Status of Functions on SW Switching

SW low/high condition

Low: GND to DVC – 1.2V

High: DVC + 1.2V to Vcc

The VC buffer is always in active mode

even if it enters sleep mode.

In the function block, MODE SW is always

set to active mode.

Item

Control

voltage

VC or Hi-Z

GND

ON

OFF

ON

Active

Sleep

Active

RW

—

ROM

APC

Active/Sleep

ROM/RW