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39LF020 Datasheet(PDF) 12 Page - Silicon Storage Technology, Inc |
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39LF020 Datasheet(HTML) 12 Page - Silicon Storage Technology, Inc |
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12 / 24 page ![]() 12 Data Sheet 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 ©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395 FIGURE 8: TOGGLE BIT TIMING DIAGRAM FIGURE 9: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM 395 ILL F07.0 ADDRESS AMS-0 DQ6 WE# OE# CE# TOE TOEH TCE TOES TWO READ CYCLES WITH SAME OUTPUTS Note: AMS = Most significant address AMS =A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040 334 ILL F08.0 ADDRESS AMS-0 DQ7-0 WE# SW0 SW1 SW2 SW3 SW4 SW5 5555 2AAA 2AAA 5555 5555 55 30 55 AA 80 AA SAX OE# CE# SIX-BYTE CODE FOR SECTOR-ERASE TSE TWP Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchageable as long as minmum timings are met. (See Table 10) SAX = Sector Address AMS = Most significant address AMS =A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040 |
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