STA3398 datasheet(64/77 Pages) STMICROELECTRONICS

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6.15

Fault detect recovery constant registers (addr 0x2B - 0x2C)

FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is asserted, the

TRISTATE output is immediately asserted low and held low for the time period specified by

this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The

default value of 0x000C gives approximately 0.1 ms.

6.16

Device status register (addr 0x2D)

This read-only register provides fault- and thermal-warning status information from the

power control block. Logic value 1 for faults or warning means normal state. Logic 0 means

a fault or warning has been detected on the power bridge. The PLLUL = 1 means that the

PLL is not locked.

FDRC15

FDRC14

FDRC13

FDRC12

FDRC11

FDRC10

FDRC9

FDRC8

000

FDRC7

FDRC6

FDRC5

FDRC4

FDRC3

FDRC2

FDRC1

FDRC0

110

PLLUL

FAULT

UVFAULT

OVFAULT

OCFAULT

OCWARN

TFAULT

TWARN

Table 73.

Status register bits

Bit

R/W

RST

Name

Description

PLLUL

PLL locked

1: PLL not locked

FAULT

0: fault detected on power bridge

1: normal operation

UVFAULT

0: VCCxX internally detected

1: undervoltage threshold

OVFAULT

0: VCCxX internally detected

1: overvoltage threshold

OCFAULT

0: overcurrent fault detected

OCWARN

0: overcurrent warning

TFAULT

0: thermal fault, junction temperature over limit

TWARN

0: thermal warning, junction temperature is close to

fault condition

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