STA3398 datasheet(65/77 Pages) STMICROELECTRONICS

65 / 77 page

STA339BW

Doc ID 15251 Rev 5

65/77

6.17

EQ coefficients and DRC configuration register (addr 0x31)

Bits AMGC[3:2] change the behavior of the bits AMGC[1:0] as given in Table 75 below.

When AMGC[3:2] = 01 then the bits 1:0 are defined as given here in Table 76.

AC0, AC1, AC2 settings are designed for the loudspeaker protection function, limiting at the

minimum any audio artefacts introduced by typical anti-clipping/DRC algorithms. More

detailed information is available in the applications notes “Configurable output power rate

using STA335BW” and “STA335BWS vs STA335BW”.

Bit XOB can be used to bypass the crossover filters. Logic 1 means that the function is not

active. In this case, high pass crossover filter works as a passtrough on the data path

(b0 = 1, all the other coefficients at logic 0) while the low pass filter is configured to have

zero signal on channel-3 data processing (all the coefficients are at logic 0).

6.18

Extended configuration register (addr 0x36)

Extended configuration register provides access to B2DRC and biquads 5, 6 and 7.

XOB

Reserved

AMGC[3]

AMGC[2]

Reserved

SEL[1]

SEL[0]

000

Table 74.

EQ RAM select

SEL[1:0]

EQ RAM bank selected

00/11

Bank 0 activated

Bank 1 activated

Bank 2 activated

Table 75.

Anti-clipping and DRC preset

AMGC[3:2]

Anti-clipping and DRC preset selected

DRC/Anti-clipping behavior described in Table 55 on page 47 (default).

DRC/Anti-clipping behavior is described in Table 76 below

10/11

Reserved, do not use

Table 76.

Anti-clipping selection for AMGC[3:2] = 01

AMGC[1:0]

Mode

AC0, stereo anticlipping 0 dB limiter

AC1, stereo anticlipping +1.25 dB limiter

AC2, stereo anticlipping +2 dB limiter

Reserved do not use

Mdrc[1]

Mdrc[0]

PS48DB

XAR1

XAR2

BQ5

BQ6

BQ7

000

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