STA3398 datasheet(47/77 Pages) STMICROELECTRONICS

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STA339BW

Doc ID 15251 Rev 5

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6.8

Audio preset registers (addr 0x0B and 0x0C)

6.8.1

Audio preset register 1 (addr 0x0B)

Using AMGC[3:0] bits, attack and release thresholds and rates are automatically configured

to properly fit application specific configurations. AMGC[3:2] is defined in register EQ

coefficients and DRC configuration register (addr 0x31) on page 65.

The AMGC[1:0] bits behave in two different ways depending on the value of AMGC[3:2].

When this value is 00 then bits AMGC[1:0] are defined below in Table 55.

6.8.2

Audio preset register 2 (addr 0x0C)

01100001 (0x61)

-0.5 dB

……

11010111 (0xD7)

-59.5 dB

11011000 (0xD8)

-60 dB

11011001 (0xD9)

-61 dB

11011010 (0xDA)

-62 dB

……

11101100 (0xEC)

-80 dB

11101101 (0xED)

Hard channel mute

……

11111111 (0xFF)

Hard channel mute

Table 54.

Channel volume as a function of CxV[7:0] (continued)

CxV[7:0]

Volume

Reserved

AMGC[1]

AMGC[0]

Reserved

000

Table 55.

Audio preset gain compression/limiters selection for AMGC[3:2] = 00

AMGC[1:0]

Mode

User programmable GC

AC no clipping 2.1

AC limited clipping (10%) 2.1

DRC night-time listening mode 2.1

XO3

XO2

XO1

XO0

AMAM2

AMAM1

AMAM0

AMAME

000

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