RT9730 datasheet(8/9 Pages) RICHTEK

8 / 9 page

RT9730

DS9730-01 April 2011

www.richtek.com

Figure 3. Derating Curves for RT9730 Packages

Layout Consideration

The RT9730 is a protection device. Careful PCB layout is

necessary. For best performance, place all peripheral

components as close to the IC as possible. A short

connection is highly recommended. The following

guidelines should be strictly followed when designing a

PCB layout for the RT9730.

The exposed pad, GND, must be soldered to a large

ground plane for heat sinking and noise prevention. The

through-hole vias located at the exposed pad is

connected to the ground plane of internal layer.

ACIN traces should be wide to minimize inductance and

handle the high currents. The trace running from input

to chip should be placed carefully and shielded strictly.

The capacitors must be placed close to the part. The

connection between pins and capacitor pads should be

copper traces without any through-hole via connection.

Figure 4. PCB Layout Guide

To Battery

To Baseband

Gate Controller

Input capacitor must be

placed between GND

and ACIN to reduce

noise.

The capacitor must be

placed between GND

and CHRIN to reduce

noise.

From Adapter

To Baseband

Charger Controller

CIN

GND

ACIN

OUT

CHRIN

GND

GATDRV

The exposed pad and

GND should be connected

to a strong ground plane

for heat sinking and noise

prevention.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

PD(MAX) = (TJ(MAX)

− TA) / θJA

where TJ(MAX) is the maximum junction temperature, TAis

the ambient temperature, and

θJA is the junction to ambient

thermal resistance.

For recommended operating condition specifications of

the RT9730, the maximum junction temperature is 125

°C

and TA is the ambient temperature. The junction to ambient

thermal resistance,

θJA, is layout dependent. For WDFN-

8L 2x2 packages, the thermal resistance,

θJA, is

120

°C/W on a standard JEDEC 51-7 four-layer thermal

test board. The maximum power dissipation at TA= 25

°C

can be calculated by the following formula :

PD(MAX) = (125

°C − 25°C) / (120°C/W) = 0.833W for

WDFN-8L 2x2 package

The maximum power dissipation depends on the operating

ambient temperature for fixed TJ(MAX) and thermal

resistance,

θJA. For the RT9730 package, the derating

curve in Figure 3 allows the designer to see the effect of

rising ambient temperature on the maximum power

dissipation.

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

100

125

Ambient Temperature (°C)

Four-Layer PCB

RT9730 Datasheet(PDF) 8 Page - Richtek Technology Corporation

RT9730 Datasheet(HTML) 8 Page - Richtek Technology Corporation

Html Pages

1 2 3 4 5 6 7 8 9

Datasheet Download

Link URL