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ACPL-024L Datasheet(PDF) 7 Page - AVAGO TECHNOLOGIES LIMITED

Part # ACPL-024L
Description  Low Power, 5 MBd Digital CMOS Optocoupler
PDF  11 Pages
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Manufacturer  AVAGO [AVAGO TECHNOLOGIES LIMITED]
Direct Link  http://www.avagotech.com
Logo AVAGO - AVAGO TECHNOLOGIES LIMITED

ACPL-024L Datasheet(HTML) 7 Page - AVAGO TECHNOLOGIES LIMITED

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Switching Specifications (AC)
Over recommended temperature (TA = -40° C to +105° C), supply voltage (2.7 V ≤ VDD ≤ 5.5 V). All typical specifications
are at VDD = 2.7 V, TA = 25° C
Parameter
Symbol
Part Number
Min
Typ
Max
Units
Test Conditions
Propagation Delay Time to
Logic Low Output [1]
tPHL
130
250
ns
IF = 2.2 mA, CL= 15 pF,
CMOS Signal Levels
(Figure 8, 9 & 12)
Propagation Delay Time to
Logic High Output [1]
tPLH
115
250
ns
Pulse Width Distortion [2]
PWD
200
ns
Propagation Delay Skew [3]
tPSK
220
ns
Output Rise Time
(10% – 90%)
tR
11
ns
IF = 2.2 mA, CL= 15 pF,
CMOS Signal Levels.
Output Fall Time
(90% – 10%)
tF
11
ns
IF = 2.2 mA, CL= 15 pF,
CMOS Signal Levels.
Static Common Mode
Transient Immunity at
Logic High Output [4]
|CMH|25
40
kV/
s
VCM = 1000 V, TA = 25° C,
IF = 2.2 mA, CL= 15 pF, VI = 5 V
(RT = 1.6 k
) or VI = 3.3 V
(RT = 840
)
CMOS Signal Levels
Figure 13
Static Common Mode
Transient Immunity at
Logic Low Output [5]
|CML|25
40
kV/
s
VCM = 1000 V, TA = 25° C,
IF = 0 mA, CL= 15 pF, VI = 0 V
(RT = 1.6 k
) or (RT = 840 )
CMOS Signal Levels
Figure 13
Notes:
1. tPHL propagation delay is measured from the 50% (Vin or IF) on the falling edge of the input pulse to the 50% VDD of the falling edge of the VO signal.
tPLH propagation delay is measured from the 50% (Vin or IF) on the rising edge of the input pulse to the 50% level of the rising edge of the VO signal
2. PWD is defined as |tPHL - tPLH|
3. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the
recommended operating conditions.
4. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.
5. CML is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a low logic state.
6. Use of a 0.1
F bypass capacitor connected between Vdd and ground is recommended.
Package Characteristics
All typical at TA = 25° C
Parameter
Symbol
Part Number
Min
Typ
Max
Units
Test Conditions
Input-Output Insulation
VISO
ACPL-M21L/
024L/021L
3750
Vrms
RH < 50% for 1 min. TA = 25° C
Input-Output Resistance
RI-O
1012
VI-O = 500 V
Input-Output Capacitance
CI-O
0.6
pF
f = 1 MHz, TA = 25° C



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