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W78LE812 Datasheet(PDF) 14 Page - Winbond

Part # W78LE812
Description  8-BIT MTP MICROCONTROLLER
PDF  25 Pages
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Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond

W78LE812 Datasheet(HTML) 14 Page - Winbond

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W78LE812
- 14 -
B0
B1
B0 : Lock bit, logic 0 : active
B1 : MOVC inhibit,
logic 0 : the MOVC instruction in external memory
cannot access the code in internal memory.
logic 1 : no restriction.
Default 1 for each bit.
Special Setting Registers
Company ID (#DAH)
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
1
1
0
1
0
Device ID (#E0H)
1
1
1
0
0
0
0
Security Bits
0
8KB MTP ROM
Program Memory
Reserved
Security Register
0FFFFh
0000h
1FFFh
Reserved
B2
B2 : Encryption
logic 0 : the encryption logic enable
logic 1 : the encryption logic disable
Lock bit
This bit is used to protect the customer's program code in the W78LE812. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
MTP ROM data and Special Setting Registers can not be accessed again.
MOVC Inhibit
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set
to logic 0, a MOVC instruction in external program memory space will be able to access code only in
the external memory, not in the internal memory. A MOVC instruction in internal program memory
space will always be able to access the ROM data in both internal and external memory. If this bit is
logic 1, there are no restrictions on the MOVC instruction.
Encryption
This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is
enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will
reset this bit.
P1
P3.0
P3.1
P3.2
P3.3
P3.6
P3.7
X'tal1
X'tal2
P0
EA/Vpp
ALE
RST
PSEN
P2
Vss
A0 to A7
V CP
V IL
V IH
V IL
V IL
V IL
V IL
V IL
A8 to A15
PGM DATA
V IH
V IH
+5V
Programming Configuration
P1
P3.0
P3.1
P3.2
P3.3
P3.6
P3.7
X'tal1
X'tal2
P0
EA/Vpp
ALE
RST
PSEN
P2
Vss
A0 to A7
V CP
V IL
V IH
V IL
V IL
V IL
V IL
V IL
A8 to A15
PGM DATA
V IH
V IH
+5V
Programming Verification
V DD
V DD



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