AD1833 datasheet(14/20 Pages) AD

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AD1833

–14–

Packed Mode 128

In Packed Mode 128, all six data channels are “packed” into

one sample interval on one data pin. The BCLK runs at 128

fS; therefore there are 128 BCLK periods in each sample inter-

val. Each sample interval is broken into eight time slots, six slots

of 20 BCLKs and two of four BCLKs. The data length is restricted

in this mode to a maximum of 20 bits. The three left channels

are written first, MSB first, and the data is written on the falling

edge of BCLK. After the three left channels are written, there is

a space of four BCLKs and then the three right channels are

written. The L/

RCLK defines the left and right data transmis-

sion; it is high for the three left channels and low for the three

right channels.

Packed Mode 256

In Packed Mode 256 all six data channels are “packed” into one

sample interval on one data pin. The BCLK runs at 256

× f

therefore there are 256 BCLK periods in each sample interval.

Each sample interval is broken into eight time slots of 32 BCLKs

each. The data length can be 16, 20, or 24 bits. The three left

channels are written first, MSB first, and the data is written on

the falling edge of BCLK with a one BCLK period delay from

the start of the slot. After the three left channels are written,

there is a space of 32 BCLKs and then the three right channels

are written. The L/

RCLK defines the left and right data trans-

mission; it is low for the three left channels and high for the

three right channels.

SLOT 1

LEFT 0

SLOT 2

LEFT 1

SLOT 3

LEFT 2

SLOT 4

RIGHT 0

SLOT 5

RIGHT 1

SLOT 6

RIGHT 2

RCLK

BCLK

DATA

MSB

24-BIT DATA

20-BIT DATA

16-BIT DATA

BCLK

MSB

–1

MSB

–2

MSB

–3

MSB

–4

LSB

MSB

–1

MSB

–2

MSB

–3

MSB

–4

LSB

MSB

–1

MSB

–2

MSB

–3

MSB

–4

LSB

Figure 10. Packed Mode 256

SLOT 1

LEFT 0

SLOT 2

LEFT 1

SLOT 3

LEFT 2

BLANK SLOT

4 SCLKs

SLOT 4

RIGHT 0

SLOT 5

RIGHT 1

SLOT 6

RIGHT 2

BLANK SLOT

4 SCLKs

MSB

20-BIT DATA

16-BIT DATA

BCLK

MSB

–1

MSB

–2

MSB

–3

MSB

–4

LSB

MSB

–1

MSB

–2

MSB

–3

MSB

–4

LSB

BCLK

DATA

RCLK

Figure 9. Packed Mode 128

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