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AD1833 Datasheet(PDF) 4 Page - Analog Devices |
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AD1833 Datasheet(HTML) 4 Page - Analog Devices |
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4 / 20 page  REV. 0 AD1833 –4– MCLK INPUT tDMH tDML tPDRP RESET INPUT Figure 1. MCLK and RESET Timing tDLS BCLK L/ RCLK SDATA LEFT-JUSTIFIED MODE SDATA RIGHT-JUSTIFIED MODE LSB SDATA I2S-JUSTIFIED MODE tDBH tDBL tDDS MSB MSB-1 tDDH tDDS MSB tDDH tDDS tDDS tDDH tDDH MSB 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 16-BIT CLOCKS (16-BIT DATA) Figure 2. Serial Data Port Timing DIGITAL TIMING (Guaranteed over –40 C to +85 C, AVDD = DVDD = 5.0 V 10%) Min Unit tDML MCLK LO Pulsewidth (All Modes) 15 ns tDMH MCLK HI Pulsewidth (All Modes) 15 ns tDBH BCLK HI Pulsewidth 15 ns tDBL BCLK LO Pulsewidth 15 ns tDLS LRCLK Setup 5 ns tDLH LRCLK Hold (DSP Serial Port Mode Only) 10 ns tDDS SDATA Setup 5 ns tDDH SDATA Hold 15 ns tPDRP PD/RST LO Pulsewidth 10 ns tCCH CCLK HI Pulsewidth 10 ns tCCL CCLK LO Pulsewidth 10 ns tCSU CDATA Setup Time 5 ns tCHD CDATA Hold Time 10 ns tCLH CLATCH HI Pulsewidth 10 ns Specifications subject to change without notice. |
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