AD1819B

–18–

REV. 0

Sample Rate 0 (Index 78h)

g

e

R

m

u

N

e

m

a

N5

1

D4

1

D3

1

D2

1

D1

1

D0

1

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Dt

l

u

a

f

e

D

h

8

70

e

t

a

R

e

l

p

m

a

S5

1

0

R

S4

1

0

R

S3

1

0

R

S2

1

0

R

S1

1

0

R

S0

1

0

R

S9

0

R

S8

0

R

S7

0

R

S6

0

R

S5

0

R

S4

0

R

S3

0

R

S2

0

R

S1

0

R

S0

0

R

Sh

0

8

B

B

SR0 [15:0]

Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h)

in 1 Hz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable results.

Sample Rate 1 (Index 7Ah)

g

e

R

m

u

N

e

m

a

N5

1

D4

1

D3

1

D2

1

D1

1

D0

1

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Dt

l

u

a

f

e

D

h

A

71

e

t

a

R

e

l

p

m

a

S5

1

1

R

S4

1

1

R

S3

1

1

R

S2

1

1

R

S1

1

1

R

S0

1

1

R

S9

1

R

S8

1

R

S7

1

R

S6

1

R

S5

1

R

S4

1

R

S3

1

R

S2

1

R

S1

1

R

S0

1

R

Sh

0

8

B

B

SR1 [15:0]

Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h)

in 1 Hz increments. The sample rate may be multiplied by 8/7 or 10/7 by setting Bits D6 and D5 in Register 76h.

Vendor ID (Index 7Ch–7Eh)

g

e

R

m

u

N

e

m

a

N5

1

D4

1

D3

1

D2

1

D1

1

D0

1

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Dt

l

u

a

f

e

D

h

C

71

D

I

r

o

d

n

e

V7

F6

F5

F4

F3

F2

F1

F0

F7

S6

S5

S4

S3

S2

S1

S0

Sh

4

4

1

4

S [7:0]

This register is ASCII encoded to “A.”

F [7:0]

This register is ASCII encoded to “D.”

g

e

R

m

u

N

e

m

a

N5

1

D4

1

D3

1

D2

1

D1

1

D0

1

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Dt

l

u

a

f

e

D

h

E

72

D

I

r

o

d

n

e

V7

T6

T5

T4

T3

T2

T1

T0

T7

V

E

R6

V

E

R5

V

E

R4

V

E

R3

V

E

R2

V

E

R1

V

E

R0

V

E

Rh

3

0

3

5

T [7:0]

This register is ASCII encoded to “S.”

REV [7:0]

Revision Register field contains the revision number.

These bits are read-only and should be verified before accessing vendor-defined features.

DIGITAL INTERFACE

AD1819B AC-Link Digital Serial Interface Protocol

The AD1819B incorporates an AC'97 5-pin digital serial interface that links it to a digital controller. AC-Link is a bidirectional, fixed

rate, serial PCM digital stream. It handles multiple input, and output audio streams, as well as control register accesses employing a

time division multiplexed (TDM) scheme. The AC-Link architecture divides each audio frame into 12 outgoing and 12 incoming

data streams, up to 20-bit sample resolution. The AD1819B uses 16-bit samples. The data streams include:

AC ’97 Protocol

•

TAG

1 Input and Output

•

Control

2 Output Slots

Control Register Write Port

•

Status

2 Input Slots

Control Register Read Port

•

PCM Playback

2 Output Slots

2-Channel Composite PCM Output Stream

•

PCM Record Data

2 Input Slots

2-Channel Composite PCM Input Stream

Synchronization of all AC-Link data transactions is signaled by the AC’97 controller. The AD1819B drives the serial bit clock onto

AC-Link, which the AC’97 controller then qualifies with a synchronization signal to construct audio frames.

SYNC, which is fixed at 48 kHz, is derived by dividing down the serial bit clock (BIT_CLK) by 256. The BIT_CLK is fixed at

12.288 MHz. AC-Link serial data is updated on each rising edge of BIT_CLK. The receiver of AC-Link data, the AD1819B for outgo-

ing data and the AC’97 controller for incoming data, samples each serial bit on the falling edge of BIT_CLK. SYNC must remain

high for a minimum of 1 BIT_CLK up to a maximum duration of 16 BIT_CLKs at the beginning of each audio frame. The first 16

bits of the audio frame is defined as the “Tag Phase.” The remainder of the audio frame is the “Data Phase.” The AD1819B uses

SYNC to define the beginning of the audio frame.