AD1868

REV. A

–7–

TIMING

Figure 10 illustrates the specific timing requirements that must

be met in order for the data transfer to be accomplished prop-

erly. The input pins of the AD1868 are TTL and 5 V CMOS

compatible.

The maximum clock rate of the AD1868 is specified to be at

least 13.5 MHz. This clock rate allows data transfer rates of 2

×,

4

×, 8×, and 16× F

tions section of this data sheet contains additional guidelines for

using the AD1868.

LSB

(18th BIT)

>15ns

CLK

> 74./ ns

>10ns

>30ns

>30ns

DATA

LATCH

ENABLE (LE)

>60ns

>40ns

>40ns

>30ns

BITS CLOCKED

TO SHIFT REGISTER

2nd BIT

MSB

1st BIT

NEXT

WORD

>10ns

INTERNAL DAC INPUT REGISTER

UPDATED WITH 18 MOST RECENT BITS

Figure 10. Input Signal Timing

APPLICATIONS OF THE AD1868

The AD1868 is a high performance audio DAC specifically de-

signed for portable and automotive digital audio applications.

These market segments have technical requirements fundamen-

tally different than those found in the high-end or home-use

market segments. Portable equipment must rely on components

which require low amounts of power to offer reasonable playing

times. Also, battery voltages drop as the end of the discharge

cycle is approached. The AD1868’s ability to operate from a

single +5 V supply makes it a good choice for battery-operated

gear. As the battery voltage drops, the power dissipation of the

AD1868 drops. This extends the usable battery life. Finally, as

the battery supply voltage drops, the bias voltages and signal

swings also drop, preventing signal clipping and abrupt degra-

dation of distortion. Figure 3 illustrates that THD+N perfor-

mance of the AD1868 remains constant through a wide range

of supply voltages.

Automotive equipment rely on components which are able to

consistently perform in a wide range of temperatures. In addi-

tion, due to the limited space available in automotive applica-

tions, small size is essential. The AD1868 is able to satisfy both

of these requirements. The device has guaranteed specified per-

formance between 0

°C and +70°C, and the 16-pin DIP or 16-

pin SOIC package is particularly attractive where overall size is

important.

Since the AD1868 provides dc bias voltages, the entire signal

chain can be dc-coupled. This eliminate ac-coupling capacitors

from the signal path, improving low frequency performance and

lowering system cost and size.

In summary, the AD1868 is an excellent choice for battery op-

erated portable or automotive digital audio systems. In the fol-

lowing sections, some examples of high performance audio

applications featuring the AD1868 are described.

AD1868 with Sony CXD2550P Digital Filter

Figure 11 illustrates an 18-bit CD player design incorporating

an AD1868 DAC, a Sony CXD2550P digital filter and 2-pole

antialias filters. This high performance, single supply design op-

erates at 8

× F

plications. In this design, the CXD2550P filter transmits left

and right channel digital data to the AD1868. The left and

right latch signals, LL and LR, are both provided by the word

clock signal (LRCKO) of the digital filter. The digital data is

converted to low distortion output voltages by the output

amplifiers on the AD1868. Also, no deglitching circuitry or

external adjustments are required. Bypass capacitors, noise

reduction capacitors and the antialias filter details are omitted

for clarity.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

16

15

LL

DL

CK

DR

LR

DGND

NRL

AGND

NRR

V

L

V

AD1868

1

2

3

4

5

6

7

8

11

12

13

14

15

16

18

17

TEST

SLOT

LRCK0

CXD2550P

9

10

V

DD

BCKO

DATAR

DATAL

1

2

3

4

5

6

8

7

AGND

V

S

LEFT

CHANNEL

OUTPUT

RIGHT

CHANNEL

OUTPUT

+5V POWER

SUPPLY

8Fs/4Fs

INIT

V

SS

V

S

V

V

V

V

S

Figure 11. AD1868 with Sony CXD2550P Digital Filter