AD1878/AD1879

REV. 0

–13–

DATA OUTPUT

BCK OUTPUT (64•F

S

)

CLOCK INPUT

LRCK OUTPUT

WCK INPUT

PREVIOUS

NEW

1

t

DLYCK

t

WSET

t

WHLD

t

DLYD,MSB

MSB

MSB–2

MSB–1

t

DLYD

t

DLYD

t

DLYCK

t

DLYCK

t

DLYCK

ZEROS

W+1 W+2 W+3

W

Figure 16. AD1878/AD1879 Master Mode Clock Timing: WCK Input

DATA OUTPUT

BCK INPUT (64•F

S

)

CLOCK INPUT

LRCK INPUT

WCK INPUT

t

HLD

t

SET

L+1

L

W+1 W+2 W+3

W

t

WSET

t

WHLD

t

DLYD,MSB

MSB

MSB–2

MSB–1

t

DLYD

t

DLYD

t

SET

t

SET

t

HLD

B+1 B+2

B

B+3

L+30 L+31

t

HLD

ZEROS

Figure 17. AD1878/AD1879 Slave Mode Timing

For slave modes, the word clock (WCK) input has the same

clock (CLOCK at “W” ) as in Figure 16 and a corresponding

the setup edge. The MSB of the DATA output will be delayed

Subsequent bits of the DATA output in contrast will be delayed

Synchronizing Multiple AD1878/AD1879s

Multiple AD1878/AD1879s can be synchronized either by

making all AD1878/AD1879s serial port slaves or by making

one AD1879 the serial port master and all other AD1879s

slaves. These two options are illustrated in Figure 18.

As a third alternative, it is possible to synchronize multiple mas-

ters all in Master Mode—Word Clock Output mode. See the

“Reset” discussion above in the “Operating Features” section

for timing considerations.

AD1878/AD1879 to DSP56001 Interface

The 18-bit AD1878/AD1879 can be interfaced quite simply to

the DSP56001 Digital Signal Processor. Figure 19 illustrates

one method of connection. In this implementation, the AD1878/

AD1879 is configured to operate in 64-Bit Master Mode With

Word Clock Output. Thus, the AD1878/AD1879 is the master

of the serial interface. The AD1878/AD1879 operates indepen-

dently from the DS

µPs clock. The DSP56001 serial port is

configured to operate in synchronous mode with the AD1878/

AD1879 connected to its synchronous serial interface (SSI) port.

CLOCK

SOURCE

#1

AD1879

MASTER MODE

CLK

DATA

BCK

WCK

LRCK

#2

AD1879

SLAVE MODE

CLK

DATA

BCK

WCK

LRCK

#N

AD1879

SLAVE MODE

CLK

DATA

BCK

WCK

LRCK

CLOCK

SOURCE

#1

AD1879

SLAVE MODE

CLK

DATA

BCK

WCK

LRCK

#2

AD1879

SLAVE MODE

CLK

DATA

BCK

WCK

LRCK

#N

AD1879

SLAVE MODE

CLK

DATA

BCK

WCK

LRCK

Figure 18. Synchronizing Multiple AD1878/AD1879s