AD1878/AD1879

REV. 0

–14–

DATA

BCK

WCK

LRCK

AD1879

SRD

SCK

SC2

SC1

DSP56001

Figure 19. AD1879 to DSP56001 Interface

To configure the DSP56001 for proper operation, the CRA

register must he programmed for a 24-bit receive data register

(RX). The CRB register must be programmed with the follow-

ing conditions: receiver enabled, normal mode, continuous

clock, word length frame synch, MSB first, SCK an input, SC1

an input and SC2 an input. The PCC register must be pro-

grammed to set the SCK, SC1, SC2, and SRD pins of Port C

to operate as a serial interface rather than in general-purpose

parallel I/O mode.

When SSI detects the rising edge of the AD1878/AD1879’s

word clock (WCK), the next 24-bits on the AD1878/AD1879’s

DATA pin will be clocked into the DSP56001’s SSI receive

shift register on the falling edges of the inverted bit-clock

(BCK) signal. This data is then transferred to the RX register.

The 16-/18-bit word from the AD1879 will be located in Bits 8

through 23/21 of the RX register. Bits 0 through 7 will be

zero-filled. The user may poll Bit 7 (RDF) of the SSI status

register (SSISR) to detect when the data has been transferred

to RX. Alternatively, the RIE bit can be set, allowing an inter-

rupt to occur when the data has been transferred.

To differentiate left and right data, the SC1 pin of the SSI is an

input and is connected to the LRCK of the AD1878/AD1879.

After a data word is transferred to the RX register, the software

reads the IF1 bit in the SSISR, which contains the left/right in-

formation. In order to use the SC1 pin as indicated, the SSI

must operate in synchronous mode. An DSP56001 assembly

code fragment for this approach (with polling) is shown in

Table I.

Table I. DSP56001 Assembly Code for AD1878/AD1879 Data

Transfer

poll jclr

#7,X:$FFEE,poll

:loop until RX reg. has data

movep

X:$FFEF,al:

:transfer ADC to al register

jset

#I:X:$FFEE,left

:if LRCK=1, save left else

move

a1,X:$C000

:store right channel

jmp

poll

:wait for next input

left move

a1,Y:$C000

:store left channel

jump poll

If the SSI is set up for asynchronous operation, the SC0 and

SC1 pins are unavailable for left/right detection. If asynchro-

nous operation is essential, left/right information can be ob-

tained by synchronizing the AD1878/AD1879 with a software

reset. Coming out of reset, the AD1878/AD1879 will transmit

left channel data first. A flag maintained in software can main-

tain the synchronization.

AD1878/AD1879 PERFORMANCE GRAPHS

0

–140

24k

–80

–120

2k

–100

0

–20

–60

–40

22k

20k

18k

16k

14k

12k

10k

8k

6k

4k

FREQUENCY – Hz

Figure 20. AD1879 S/(THD+N)—1 kHz Tone at –0.5 dBFS

(4k-Point FFT)

0

–140

24k

–80

–120

2k

–100

0

–20

–60

–40

22k

20k

18k

16k

14k

12k

10k

8k

6k

4k

FREQUENCY – Hz

Figure 21. AD1879 S/(THD+N)—1 kHz Tone at –10 dBFS

(4k-Point FFT)

0

–140

24k

–80

–120

2k

–100

0

–20

–60

–40

22k

20k

18k

16k

14k

12k

10k

8k

6k

4k

FREQUENCY – Hz

Figure 22. AD1879 S/(THD+N)—1 kHz Tone at –60 dBFS

(4k-Point FFT)