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AD1885 Datasheet(PDF) 6 Page - Analog Devices |
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AD1885 Datasheet(HTML) 6 Page - Analog Devices |
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6 / 27 page  AD1885 –6– REV. 0 RESET BIT_CLK tRST2CLK tRST_LOW Figure 1. Cold Reset SYNC BIT_CLK tSYNC_HIGH tRST2CLK Figure 2. Warm Reset tCLK_HIGH BIT_CLK tCLK_LOW SYNC tSYNC_HIGH tSYNC_LOW tSYNC_PERIOD tCLK_PERIOD Figure 3. Clock Timing BIT_CLK SYNC tHOLD SDATA_OUT tSETUP Figure 4. Data Setup and Hold BIT_CLK SYNC SDATA_IN tRISECLK tRISESYNC tRISEDIN tRISEDOUT tFALLCLK tFALLSYNC tFALLDIN tFALLDOUT SDATA_OUT Figure 5. Signal Rise and Fall Time BIT_CLK SDATA_OUT SYNC SDATA_IN SLOT 1 SLOT 2 WRITE TO 0x26 DATA PR4 DON’T CARE tS2_PDOWN NOTE: BIT_CLK NOT TO SCALE Figure 6. AC-Link Low Power Mode Timing RESET SDATA_OUT HI-Z tSETUP2RST tOFF SDATA_IN, BIT_CLK Figure 7. ATE Test Mode |
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