AD1885

–19–

REV. 0

Extended Audio Status and Control Register (Index 2Ah)

g

e

Rg

e

R g

e

R g

e

Rg

e

R

m

u

Nm

u

N m

u

N m

u

Nm

u

N

e

m

a

Ne

m

a

N

e

m

a

N

e

m

a

Ne

m

a

N5

1

D5

1

D 5

1

D 5

1

D5

1

D4

1

D4

1

D 4

1

D 4

1

D4

1

D3

1

D3

1

D 3

1

D 3

1

D3

1

D2

1

D2

1

D 2

1

D 2

1

D2

1

D1

1

D1

1

D 1

1

D 1

1

D1

1

D0

1

D0

1

D 0

1

D 0

1

D0

1

D9

D9

D9

D9

D9

D8

D8

D8

D8

D8

D7

D7

D7

D7

D7

D6

D6

D6

D6

D6

D5

D5

D5

D5

D5

D4

D4

D4

D4

D4

D3

D3

D3

D3

D3

D2

D2

D2

D2

D2

D1

D1

D1

D1

D1

D0

D0

D0

D0

D0

Dt

l

u

a

f

e

Dt

l

u

a

f

e

D

t

l

u

a

f

e

D

t

l

u

a

f

e

Dt

l

u

a

f

e

D

h

A

2h

A

2 h

A

2 h

A

2h

A

2l

r

t

C

/

t

S

o

i

d

u

A

d

e

d

n

e

t

x

El

r

t

C

/

t

S

o

i

d

u

A

d

e

d

n

e

t

x

E

l

r

t

C

/

t

S

o

i

d

u

A

d

e

d

n

e

t

x

E

l

r

t

C

/

t

S

o

i

d

u

A

d

e

d

n

e

t

x

El

r

t

C

/

t

S

o

i

d

u

A

d

e

d

n

e

t

x

EX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XA

R

VA

R

V A

R

V A

R

VA

R

Vh

0

0

0

0h

0

0

0

0

h

0

0

0

0

h

0

0

0

0h

0

0

0

0

Note: The Extended Audio Status and Control Register is a read/write register that provides status and control of the extended audio

features.

VRA

Variable Rate Audio. VRA = 1 enables support for Variable Rate Audio mode (sample rate control registers and

SLOTREQ signaling).

PCM DAC Rate Register (Index 2Ch)

g

e

Rg

e

R g

e

R g

e

Rg

e

R

m

u

Nm

u

N m

u

N m

u

Nm

u

N

e

m

a

Ne

m

a

N

e

m

a

N

e

m

a

Ne

m

a

N5

1

D5

1

D 5

1

D 5

1

D5

1

D4

1

D4

1

D 4

1

D 4

1

D4

1

D3

1

D3

1

D 3

1

D 3

1

D3

1

D2

1

D2

1

D 2

1

D 2

1

D2

1

D1

1

D1

1

D 1

1

D 1

1

D1

1

D0

1

D0

1

D 0

1

D 0

1

D0

1

D9

D9

D9

D9

D9

D8

D8

D8

D8

D8

D7

D7

D7

D7

D7

D6

D6

D6

D6

D6

D5

D5

D5

D5

D5

D4

D4

D4

D4

D4

D3

D3

D3

D3

D3

D2

D2

D2

D2

D2

D1

D1

D1

D1

D1

D0

D0

D0

D0

D0

Dt

l

u

a

f

e

Dt

l

u

a

f

e

D

t

l

u

a

f

e

D

t

l

u

a

f

e

Dt

l

u

a

f

e

D

)

h

A

7

(

/

h

C

2)

h

A

7

(

/

h

C

2

)

h

A

7

(

/

h

C

2

)

h

A

7

(

/

h

C

2)

h

A

7

(

/

h

C

2e

t

a

R

C

A

D

M

C

Pe

t

a

R

C

A

D

M

C

P

e

t

a

R

C

A

D

M

C

P

e

t

a

R

C

A

D

M

C

Pe

t

a

R

C

A

D

M

C

P5

1

R

S5

1

R

S

5

1

R

S

5

1

R

S5

1

R

S4

1

R

S4

1

R

S

4

1

R

S

4

1

R

S4

1

R

S3

1

R

S3

1

R

S

3

1

R

S

3

1

R

S3

1

R

S2

1

R

S2

1

R

S

2

1

R

S

2

1

R

S2

1

R

S1

1

R

S1

1

R

S

1

1

R

S

1

1

R

S1

1

R

S0

1

R

S0

1

R

S

0

1

R

S

0

1

R

S0

1

R

S9

R

S9

R

S 9

R

S 9

R

S9

R

S8

R

S8

R

S 8

R

S 8

R

S8

R

S7

R

S7

R

S 7

R

S 7

R

S7

R

S6

R

S6

R

S 6

R

S 6

R

S6

R

S5

R

S5

R

S 5

R

S 5

R

S5

R

S4

R

S4

R

S 4

R

S 4

R

S4

R

S3

R

S3

R

S 3

R

S 3

R

S3

R

S2

R

S2

R

S 2

R

S 2

R

S2

R

S1

R

S1

R

S 1

R

S 1

R

S1

R

S0

R

S0

R

S 0

R

S 0

R

S0

R

Sh

0

8

B

Bh

0

8

B

B

h

0

8

B

B

h

0

8

B

Bh

0

8

B

B

Note: 2Ch is an alias for 7Ah. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample

rates are reset to 48 kHz.

SR[15:0]

Writing to this register allows programming of the sampling frequency from 7040 Hz (1B80h) to 48 kHz (BB80h)

in 1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (BB80h) causes the

codec to saturate. For all rates, if the value written to the register is supported, that value will be echoed back

when read, otherwise the closest rate supported is returned.

PCM ADC Rate Register (Index 32h)

g

e

Rg

e

R g

e

R g

e

Rg

e

R

m

u

Nm

u

N m

u

N m

u

Nm

u

N

e

m

a

Ne

m

a

N

e

m

a

N

e

m

a

Ne

m

a

N5

1

D5

1

D 5

1

D 5

1

D5

1

D4

1

D4

1

D 4

1

D 4

1

D4

1

D3

1

D3

1

D 3

1

D 3

1

D3

1

D2

1

D2

1

D 2

1

D 2

1

D2

1

D1

1

D1

1

D 1

1

D 1

1

D1

1

D0

1

D0

1

D 0

1

D 0

1

D0

1

D9

D9

D9

D9

D9

D8

D8

D8

D8

D8

D7

D7

D7

D7

D7

D6

D6

D6

D6

D6

D5

D5

D5

D5

D5

D4

D4

D4

D4

D4

D3

D3

D3

D3

D3

D2

D2

D2

D2

D2

D1

D1

D1

D1

D1

D0

D0

D0

D0

D0

Dt

l

u

a

f

e

Dt

l

u

a

f

e

D

t

l

u

a

f

e

D

t

l

u

a

f

e

Dt

l

u

a

f

e

D

)

h

8

7

(

/

h

2

3)

h

8

7

(

/

h

2

3

)

h

8

7

(

/

h

2

3

)

h

8

7

(

/

h

2

3)

h

8

7

(

/

h

2

3e

t

a

R

C

D

A

M

C

Pe

t

a

R

C

D

A

M

C

P

e

t

a

R

C

D

A

M

C

P

e

t

a

R

C

D

A

M

C

Pe

t

a

R

C

D

A

M

C

P5

1

R

S5

1

R

S

5

1

R

S

5

1

R

S5

1

R

S4

1

R

S4

1

R

S

4

1

R

S

4

1

R

S4

1

R

S3

1

R

S3

1

R

S

3

1

R

S

3

1

R

S3

1

R

S2

1

R

S2

1

R

S

2

1

R

S

2

1

R

S2

1

R

S1

1

R

S1

1

R

S

1

1

R

S

1

1

R

S1

1

R

S0

1

R

S0

1

R

S

0

1

R

S

0

1

R

S0

1

R

S9

R

S9

R

S 9

R

S 9

R

S9

R

S8

R

S8

R

S 8

R

S 8

R

S8

R

S7

R

S7

R

S 7

R

S 7

R

S7

R

S6

R

S6

R

S 6

R

S 6

R

S6

R

S5

R

S5

R

S 5

R

S 5

R

S5

R

S4

R

S4

R

S 4

R

S 4

R

S4

R

S3

R

S3

R

S 3

R

S 3

R

S3

R

S2

R

S2

R

S 2

R

S 2

R

S2

R

S1

R

S1

R

S 1

R

S 1

R

S1

R

S0

R

S0

R

S 0

R

S 0

R

S0

R

Sh

0

8

B

Bh

0

8

B

B

h

0

8

B

B

h

0

8

B

Bh

0

8

B

B

Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample

rates are reset to 48 kHz.

SR[15:0]

Writing to this register allows programming of the sampling frequency from 7040 Hz (1B80h) to 48 kHz (BB80h)

in 1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (BB80h) causes the

codec to saturate. For all rates, if the value written to the register is supported, that value will be echoed back

when read; otherwise, the closest rate supported is returned.

Jack Sense/Audio Interrupt/Status Register (Index 72h)

g

e

Rg

e

R g

e

R g

e

Rg

e

R

m

u

Nm

u

N m

u

N m

u

Nm

u

N

e

m

a

Ne

m

a

N

e

m

a

N

e

m

a

Ne

m

a

N5

1

D5

1

D 5

1

D 5

1

D5

1

D4

1

D4

1

D 4

1

D 4

1

D4

1

D3

1

D3

1

D 3

1

D 3

1

D3

1

D2

1

D2

1

D 2

1

D 2

1

D2

1

D1

1

D1

1

D 1

1

D 1

1

D1

1

D0

1

D0

1

D 0

1

D 0

1

D0

1

D9

D9

D9

D9

D9

D8

D8

D8

D8

D8

D7

D7

D7

D7

D7

D6

D6

D6

D6

D6

D5

D5

D5

D5

D5

D4

D4

D4

D4

D4

D3

D3

D3

D3

D3

D2

D2

D2

D2

D2

D1

D1

D1

D1

D1

D0

D0

D0

D0

D0

Dt

l

u

a

f

e

Dt

l

u

a

f

e

D

t

l

u

a

f

e

D

t

l

u

a

f

e

Dt

l

u

a

f

e

D

h

2

7h

2

7 h

2

7 h

2

7h

2

7

o

i

d

u

A

/

e

s

n

e

S

k

c

a

Jo

i

d

u

A

/

e

s

n

e

S

k

c

a

J

o

i

d

u

A

/

e

s

n

e

S

k

c

a

J

o

i

d

u

A

/

e

s

n

e

S

k

c

a

Jo

i

d

u

A

/

e

s

n

e

S

k

c

a

J

s

u

t

a

t

S

/

t

p

u

r

r

e

t

n

Is

u

t

a

t

S

/

t

p

u

r

r

e

t

n

I

s

u

t

a

t

S

/

t

p

u

r

r

e

t

n

I

s

u

t

a

t

S

/

t

p

u

r

r

e

t

n

Is

u

t

a

t

S

/

t

p

u

r

r

e

t

n

I

/

T

U

O

_

1

S

J/

T

U

O

_

1

S

J

/

T

U

O

_

1

S

J

/

T

U

O

_

1

S

J/

T

U

O

_

1

S

J

T

C

N

U

FT

C

N

U

F

T

C

N

U

F

T

C

N

U

FT

C

N

U

F

_

0

S

J_

0

S

J

_

0

S

J

_

0

S

J_

0

S

J

T

U

OT

U

O T

U

O T

U

OT

U

O

1

S

J1

S

J 1

S

J 1

S

J1

S

J

S

I

D

U

PS

I

D

U

P

S

I

D

U

P

S

I

D

U

PS

I

D

U

P

0

S

J0

S

J 0

S

J 0

S

J0

S

J

S

I

D

U

PS

I

D

U

P

S

I

D

U

P

S

I

D

U

PS

I

D

U

P

1

S

J1

S

J 1

S

J 1

S

J1

S

J_

_

_

_

_

E

OE

OE

OE

OE

O

0

S

J0

S

J 0

S

J 0

S

J0

S

J_

_

_

_

_

E

OE

OE

OE

OE

O

1

S

J1

S

J 1

S

J 1

S

J1

S

J

S

I

DS

I

D S

I

D S

I

DS

I

D

0

S

J0

S

J 0

S

J 0

S

J0

S

J

S

I

DS

I

D S

I

D S

I

DS

I

D

1

S

J1

S

J 1

S

J 1

S

J1

S

J

R

L

CR

L

C R

L

C R

L

CR

L

C

0

S

J0

S

J 0

S

J 0

S

J0

S

J

R

L

CR

L

C R

L

C R

L

CR

L

C

1

S

J1

S

J 1

S

J 1

S

J1

S

J

E

D

O

ME

D

O

M

E

D

O

M

E

D

O

ME

D

O

M

0

S

J0

S

J 0

S

J 0

S

J0

S

J

E

D

O

ME

D

O

M

E

D

O

M

E

D

O

ME

D

O

M

D

U

AD

U

A D

U

A D

U

AD

U

A

T

N

IT

N

I T

N

I T

N

IT

N

I

1

S

J1

S

J 1

S

J 1

S

J1

S

J0

S

J0

S

J 0

S

J 0

S

J0

S

J

S

JS

JS

JS

JS

J

T

N

IT

N

I T

N

I T

N

IT

N

I

h

0

0

0

0h

0

0

0

0

h

0

0

0

0

h

0

0

0

0h

0

0

0

0

Note: all register bits are read/write except for AUDINT, JSINT, JS0 and JS1, which are read only.

JSINT

Indicates that a jack sense interrupt has been generated by JS0 or JS1. Remains set until all JS enabled interrupts

are cleared.

JS0

Indicates Pin JS0 state.

JS1

Indicates Pin JS1 state.

AUDINT

Indicates the Codec has generated audio interrupt. Remains set until software clears all pending interrupts.

JS0MODE

Sets JS0 pin input mode, 1 = Interrupt 0 = Jack Sense.

JS1MODE

Sets JS1 pin input mode, 1 = Interrupt 0 = Jack Sense.

JS0CLR

This bit is set by the Codec when there is a pending JS0 interrupt. Software must clear this bit to clear the JS0

interrupt status bit.

JS1CLR

This bit is set by the Codec when there is a pending JS1 interrupt. Software must clear this bit to clear the JS1

interrupt status bit.

JS0DIS

If the JS0DIS bit is set, the Codec ignores Jack Sense pin JS0.

JS1DIS

If the JS1DIS bit is set, the Codec ignores Jack Sense pin JS1.