Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

AD5124 Datasheet(PDF) 11 Page - Analog Devices

Part # AD5124
Description  The AD5124/AD5144/AD5144A potentiometers provide a nonvolatile solution for 128-/256-position adjustment applications, offering guaranteed low resistor tolerance errors of 짹8% and up to 짹6 mA current density in the Ax, Bx, and Wx pins.
PDF  36 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5124 Datasheet(HTML) 11 Page - Analog Devices

Back Button AD5124 Datasheet HTML 7Page - Analog Devices AD5124 Datasheet HTML 8Page - Analog Devices AD5124 Datasheet HTML 9Page - Analog Devices AD5124 Datasheet HTML 10Page - Analog Devices AD5124 Datasheet HTML 11Page - Analog Devices AD5124 Datasheet HTML 12Page - Analog Devices AD5124 Datasheet HTML 13Page - Analog Devices AD5124 Datasheet HTML 14Page - Analog Devices AD5124 Datasheet HTML 15Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 36 page
background image
Data Sheet
AD5124/AD5144/AD5144A
Rev. A | Page 11 of 36
Parameter1
Test Conditions/Comments
Min
Typ
Max
Unit
Description
t12
Standard mode
300
ns
Fall time of SCL signal, tFCL
Fast mode
20 + 0.1 CL
300
ns
tSP3
Fast mode
0
50
ns
Pulse width of suppressed spike
1 Maximum bus capacitance is limited to 400 pF.
2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the
EMC behavior of the part.
3 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode.
Table 6. Control Pins
Parameter
Min
Typ
Max
Unit
Description
t1
1
μs
End command to LRDAC falling edge
t2
50
ns
Minimum LRDAC low time
t3
0.1
10
μs
RESET low time
tEEPROM_PROGRAM
1
15
50
ms
Memory program time (not shown in Figure 8)
tEEPROM_READBACK
7
30
μs
Memory readback time (not shown in Figure 8)
tPOWER_UP2
75
μs
Start-up time (not shown in Figure 8)
tRESET
30
μs
Reset EEPROM restore time (not shown in Figure 8)
1 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles.
2 Maximum time after VDD − VSS is equal to 2.3 V.
SHIFT REGISTER AND TIMING DIAGRAMS
DATA BITS
DB8
DB15 (MSB)
DB0 (LSB)
D7
D6
D5
D4
D3
D2
D1
D0
ADDRESS BITS
A0
A1
A2
C2
C1
C0
A3
C3
CONTROL BITS
DB7
Figure 4. Input Shift Register Contents
t7
t6
t2
t4
t11
t12
t6
t5
t10
t1
SCL
SDA
PS
S
P
t3
t8
t9
Figure 5. I2C Serial Interface Timing Diagram (Typical Write Sequence)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com