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AD5124 Datasheet(PDF) 14 Page - Analog Devices |
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AD5124 Datasheet(HTML) 14 Page - Analog Devices |
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14 / 36 page ![]() AD5124/AD5144/AD5144A Data Sheet Rev. A | Page 14 of 36 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 GND A1 W1 W3 A3 B1 SYNC A2 VSS B3 20 19 18 17 16 15 14 13 12 11 SDI SCLK VLOGIC W4 B4 VDD W2 B2 A4 SDO AD5124/ AD5144 TOP VIEW (Not to Scale) Figure 9. 20-Lead TSSOP, SPI Interface Pin Configuration (AD5124/AD5144) Table 9. 20-Lead TSSOP, SPI Interface Pin Function Descriptions (AD5124/AD5144) Pin No. Mnemonic Description 1 SYNC Synchronization Data Input, Active Low. When SYNC returns high, data is loaded into the input shift register. 2 GND Ground Pin, Logic Ground Reference. 3 A1 Terminal A of RDAC1. VSS ≤ VA ≤ VDD. 4 W1 Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD. 5 B1 Terminal B of RDAC1. VSS ≤ VB ≤ VDD. 6 A3 Terminal A of RDAC3. VSS ≤ VA ≤ VDD. 7 W3 Wiper Terminal of RDAC3. VSS ≤ VW ≤ VDD. 8 B3 Terminal B of RDAC3. VSS ≤ VB ≤ VDD. 9 VSS Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. 10 A2 Terminal A of RDAC2. VSS ≤ VA ≤ VDD. 11 W2 Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD. 12 B2 Terminal B of RDAC2. VSS ≤ VB ≤ VDD. 13 A4 Terminal A of RDAC4. VSS ≤ VA ≤ VDD. 14 W4 Wiper Terminal of RDAC4. VSS ≤ VW ≤ VDD. 15 B4 Terminal B of RDAC4. VSS ≤ VB ≤ VDD. 16 VDD Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. 17 VLOGIC Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. 18 SCLK Serial Clock Line. Data is clocked in at the logic low transition. 19 SDI Serial Data Input. 20 SDO Serial Data Output. This is an open-drain output pin, and it needs an external pull-up resistor. |
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