AD1890/AD1891

REV. 0

–19–

BCLK_I, BCLK_O

NORMAL MODE

BCLK_I, BCLK_O

INVERTED MODE

INPUT

DATA IN/OUT

NO MSB DELAY MODE

MSB–2 MSB–3

LEFT DATA

MSB

MSB-1

RIGHT DATA

LSB+1

LSB

MSB-3

MSB

MSB-1 MSB-2

LSB

DATA IN/OUT

MSB DELAY MODE

MSB

MSB–1 MSB–2

LEFT DATA

MSB

LSB

LSB+1

LSB+2

MSB-1 MSB-2

RIGHT DATA

LSB+1

LSB

LR_I, LR_O

INPUT

Figure 23. AD1890/AD1891 Serial Data Input and Output Timing, Left/Right Clock Triggered Mode

MCLK

RESET

Figure 25. AD1890/AD1891 Reset Timing

MCLK

t

MCLK

t

MPWL

t

MPWH

Figure 24. AD1890/AD1891 MCLK Timing

t

DH

BCLK_I, BCLK_O

NORMAL MODE

BCLK_I, BCLK_O

INVERTED MODE

WCLK_I

WCLK_O

t

BPWH

MSB

MSB-1

DATA IN

NO MSB DELAY MODE

DATA OUT

NO MSB DELAY MODE

DATA IN

MSB DELAY MODE

DATA OUT

MSB DELAY MODE

t

DOH

MSB

MSB

MSB-1

t

BPWL

t

BPWL

t

BPWH

t

LRSO

t

DS

t

LRSI

t

WSO

t

WSI

t

DH

t

DPD

MSB-1

MSB

t

DS

t

DOH

MSB-1

t

DPD

LR_I

LR_O

Figure 26. AD1890/AD1891 Bit Clock, Word Clock, Left/Right Clock and Data Timing