REV. F

–8–

AD420

THREE-WIRE INTERFACE

Figure 8 shows the AD420 connected in the three-wire interface

mode. The AD420 data input block contains a serial input shift

register and a parallel latch. The contents of the shift register are

controlled by the DATA IN signal and the rising edges of the

CLOCK. Upon request of the LATCH pin the DAC and inter-

nal latch are updated from the shift register parallel outputs.

The CLOCK should remain inactive while the DAC is updated.

Refer to the timing requirements for three-wire interface.

FAULT

DETECT

LATCH

CLOCK

DATA

IN

GND

DATA

OUT

AD420

DAC1

LATCH

FAULT

DETECT

CLOCK

DATA

IN

GND

DATA

OUT

AD420

DAC2

10k

FAULT DETECT

LATCH

CLOCK

DATA IN

Figure 8. Three-Wire Interface Using Multiple DACs with

Joint Fault Detect

USING MULTIPLE DACS WITH FAULT DETECT

The three-wire interface mode can utilize the serial DATA

OUT for easy interface to multiple DACs. To program the two

AD420s in Figure 8, 32 data bits are required. The first 16 bits

are clocked into the input shift register of DAC1. The next 16

bits transmitted pass the first 16 bits from the DATA OUT pin

of DAC1 to the input register of DAC2. The input shift regis-

ters of the two DACs operate as a single 32-bit shift register,

with the leading 16 bits representing information for DAC2 and

the trailing 16 bits serving for DAC1. Each DAC is then up-

dated upon request of the LATCH pin. The daisy-chain can be

extended to as many DACs as required.

ASYNCHRONOUS INTERFACE USING OPTOCOUPLERS

The AD420 connected in ASYNCHRONOUS INTERFACE

mode with optocouplers is shown in Figure 9. Asynchronous

operation minimizes the number of control signals required for

isolation of the digital system from the control loop. The resistor

50 k

Ω pull-up resistor, from 18 V–32 V use 100 kΩ. Asynchro-

nous mode requires that the clock run at 16 times the data bit

rate, therefore to operate at the maximum input data rate of

150 kBPS an input clock of 2.4 MHz is required. The actual

data rate achieved may be limited by the type of optocouplers

chosen. The number of control signals can further be reduced

by creating the appropriate clock signal on the current loop side

of the isolation barrier. If optocouplers with relatively slow rise

and fall times are used, Schmitt triggers may be required on the

digital inputs to prevent erroneous data being presented to the

DAC.

GND

LATCH

CLOCK

DATA IN

CLOCK

+5V

DATA

ISOLATION

GALVANIC

BARRIER

+24V

11

2

8

23

7

9

100k

AD420

Figure 9. Asynchronous Interface Using Optocouplers