REV. F

–4–

AD420

THREE-WIRE INTERFACE

CLOCK

DATA IN

LATCH

DATA OUT

CLOCK

DATA IN

LATCH

DATA OUT

WORD "N"

WORD "N + 1"

WORD "N – 1"

WORD "N"

1

0

1 1

0 0

1

0 0

1 1 1

0 0

1 1

1

0 0

1

1 01 1

Figure 2. Timing Diagram for Three-Wire Interface

Table II. Timing Specification for Three-Wire Interface

Parameter

Label

Limit

Units

Data Clock Period

300

ns min

Data Clock Low Time

80

ns min

Data Clock High Time

80

ns min

Data Stable Width

125

ns min

Data Setup Time

40

ns min

Data Hold Time

5

ns min

Latch Delay Time

80

ns min

Latch Low Time

80

ns min

Latch High Time

80

ns min

Serial Output Delay Time

225

ns max

Clear Pulsewidth

50

ns min

Three-Wire Interface Fast Edges on Digital Input

With a fast rising edge (<10 ns) on one of the serial inputs

(CLOCK, DATA IN, LATCH) while another input is logic

high, the part may be triggered into a test mode and the con-

tents of the data register may become corrupted, which may

result in the output being loaded with an incorrect value. If fast

edges are expected on the digital input lines, it is recommended

that the latch line remain at Logic 0 during serial loading of the

DAC. Similarly, the clock line should remain low during updates

of the DAC via the latch pin. Alternatively, the addition of

small value capacitors on the digital lines will slow down the

edge.

CLOCK

DATA IN

CLOCK

DATA IN

01

1

0

0

(INTERNALLY GENERATED LATCH)

EXPANDED TIME VIEW BELOW

CLOCK COUNTER STARTS HERE

CONFIRM START BIT

SAMPLE BIT 15

0

1

2

8

16

24

START BIT

DATA BIT 15

BIT 14

EXPANDED TIME VIEW BELOW

CLOCK

DATA IN

Figure 3. Timing Diagram for Asynchronous Interface

Table III. Timing Specifications for Asynchronous Interface

Parameter

Label Limit Units

Asynchronous Clock Period

400

ns min

Asynchronous Clock Low Time

50

ns min

Asynchronous Clock High Time

150

ns min

300

ns min

Data Setup Time (Critical Clock Edge)

50

ns min

Data Hold Time (Critical Clock Edge)

20

ns min

Clear Pulsewidth

50

ns min

ASYNCHRONOUS INTERFACE

Note in the timing diagram for asynchronous mode operation

each data word is “framed” by a START (0) bit and a STOP

(1) bit. The data timing is with respect to the rising edge of the

CLOCK at the center of each bit cell. Bit cells are 16 clocks

long, and the first cell (the START bit) begins at the first clock

following the leading (falling) edge of the START bit. Thus the

MSB (D15) is sampled 24 clock cycles after the beginning of

the START bit, D14 is sampled at clock number 40, and so on.

During any “dead time” before writing the next word the

DATA IN pin must remain at Logic 1.

The DAC output updates when the STOP bit is received. In

the case of a “framing error” (the STOP bit sampled as a 0) the

AD420 will output a pulse at the DATA OUT pin one clock

period wide during the clock period subsequent to sampling the

STOP bit. The DAC output will not update if a “framing error”

is detected.