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PRELIMINARY TECHNICAL DATA

Nonvolatile Memory Digital Potentiometers

AD5235

REV PrD 6 NOV, 2000

Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the

information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara,

CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com

RWA(Dx) = [ (2

N-Dx)/2N ] * R

AB + RW

eqn. 3

Similarly, eqn. 3 becomes:

RWA(Dx) = [ (1024-Dx)/1024 ] * RAB + 50Ω

eqn. 4

For example, when VA = 0V and B–terminal is tied to the wiper W

the following output resistance values will be set for the following

RDAC latch codes (applies to RAB=10KΩ potentiometers):

RWA

Output State

(DEC)

(

Ω)

1023

Full-Scale

512

12500

Mid-Scale

25000

1 LSB

25050

Zero-Scale

A ±1% typical distribution of RAB from channel-to-channel occurs

within the same package. On the other hand, device to device

matching is process lot dependent such that a maximum of ±30%

variation is possible. The change in RAB with temperature has a 50

ppm/°C temperature coefficient.

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates an output voltage

proportional to the input voltage applied to a given terminal. For

example connecting A–terminal to +5V and B–terminal to ground

produces an output voltage at the wiper which can be any value

starting at zero volts and up to 1 LSB less than +5V. Each LSB of

voltage is equal to the voltage applied across terminal AB divided

by the 2

N resolution of the potentiometer divider. The general

equation defining the output voltage with respect to ground for any

given input voltage applied to terminals AB is:

VW(Dx) = Dx/2

N * V

AB + VBeqn. 5

Since N=10,

VW(Dx) = (Dx/1024) * VAB + VB

eqn. 6

Operation of the digital potentiometer in the divider mode results in

more accurate operation over temperature. Here the output voltage

is dependent on the ratio of the internal resistors and not the

absolute value. Therefore, the drift reduces to 15ppm/°C.

ESD PROTECTION CIRCUITS

IN P U T S

L OGIC

PINS

GN D

Figure 5A. Equivalent Digital Input ESD Protection

OU T P U T S

O1 & O2

PINS

GN D

Figure 5B. Equivalent Digital Output ESD Protection

OUT P U T S

SDO

GND

Figure 5C. Equivalent SDO Output ESD Protection Circuit

Figure 5 shows the equivalent ESD protection circuit for digital

pins. Figure 6 shows the equivalent analog-terminal protection

circuit for the variable resistors.

PO T E N T IO M E T E R

TE R M IN A L S

A, B, W

PIN S

Figure 6. Equivalent VR-Terminal ESD Protection

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