AD5235 datasheet(3/10 Pages) AD

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PRELIMINARY TECHNICAL DATA

Nonvolatile Memory Digital Potentiometers

AD5235

REV PrD 6 NOV, 2000

Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the

information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara,

CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com

ELECTRICAL CHARACTERISTICS 25K, 250K OHM VERSIONS (V

DD = +3V±10% to +5V±10% and VSS=0V, VA

= +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 5, 8)

Clock Cycle Time

t 1

Input Clock Pulse Width

t 2 , t 3

Clock level high or low

CS Setup Time

t 4

Data Setup Time

t 5

From Positive CLK transition

Data Hold Time

t 6

From Positive CLK transition

CLK Shutdown Time

t 7

CS Rise to Clock Rise Setup

t 8

CS High Pulse Width

t 9

CLK to SDO Propagation Delay9

t 10

RL = 1KΩ, CL < 20pF

Store to Nonvolatile EEMEM Save Time10 t 11

Applies to Command 2H, 3H

CS to SDO - SPI line acquire

t 12

CS to SDO - SPI line release

t 13

RDY Rise to CLK Rise

t 14

Startup Time

t 15

CLK Setup Time

t 16

For 1 CLK period (t4 - t3 = 1 CLK period)

Preset Pulse Width

tPR

NOTES:

Typicals represent average readings at +25°C and VDD = +5V.

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step

change from ideal between successive tap positions. Parts are guaranteed monotonic. See figure 20 test circuit. IW = VDD/R for both VDD=+3V or VDD=+5V.

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V.

DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions. See Figure 19 test circuit.

Resistor terminals A,B,W have no limitations on polarity with respect to each other.

Guaranteed by design and not subject to production test.

PDISS is calculated from (IDD x VDD=+5V).

All dynamic characteristics use VDD = +5V.

See timing diagram for location of measured values. All input control voltages are specified with tR=tF=2.5ns(10% to 90% of 3V) and timed from a voltage level of 1.5V. Switching characteristics are

measured using both VDD = +3V or +5V.

Propagation delay depends on value of VDD, RPULL_UP, and CL see applications text.

10.

Low only for commands 8, 9,10, 2, 3: CMD_8 ~ 1ms; CMD_9,10 ~0.1ms; CMD_2,3 ~20ms.

Timing Diagram

MS B

LS B

MS B

LS B

CL K

SDI

SDO1

RD Y

MS B

LS B

SDO2

SDO 1 CLK IDLES LOW

S DO 2 CLK IDLES HIGH

Figure 1. Timing Diagram

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