AD671

REV. B

–11–

MSB

OTR

MSB

OVER = "1"

UNDER = "1"

Figure 11. Overrange or Underrange Logic

OUTPUT DATA FORMAT

The AD671 provides both MSB and MSB outputs, delivering

data in positive true straight binary for unipolar input ranges

and positive true offset binary or twos complement for bipolar

input ranges. Straight binary coding is used for systems that ac-

cept positive-only signals. If straight binary coding is used with

bipolar input signals a 0 V input would result in a binary output

of 2048. The application software would have to subtract 2048

to determine the true input voltage. Most processors typically

perform math on signed integers and assume data is in that for-

mat. Twos complement format minimizes software overhead

which is especially important in high speed data transfers, such

as a DMA operation. The CPU is not bogged down performing

data conversion steps, hence increasing the total system

throughput.

Table III. Output Data Format

Input

Analog

Digital

Range

Coding

Input

1

Output

OTR

2

0 to +5 V

Straight Binary

≤ –0.00061 V

0000 0000 0000

1

0 V

0000 0000 0000

0

+5 V

1111 1111 1111

0

>+5.00061 V

1111 1111 1111

1

0 to +10 V

Straight Binary

≤ –0.00122 V

0000 0000 0000

1

0 V

0000 0000 0000

0

+10 V

1111 1111 1111

0

≥ +10.00122 V

1111 1111 1111

1

–5 V to +5 V

Offset Binary

≤ –5.00122 V

0000 0000 0000

1

–5 V

0000 0000 0000

0

0 V

1000 0000 0000

0

+4.99756 V

1111 1111 1111

0

≥ +4.99878 V

1111 1111 1111

1

–5 V to +5 V

2s Complement

≤ –5.00122 V

1000 0000 0000

1

(Using MSB)

–5 V

1000 0000 0000

0

0 V

0000 0000 0000

0

+4.99756 V

0111 1111 1111

0

≥ +4.99878 V

0111 1111 1111

1

NOTES

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

1k

10k

100k

1M

10M

CONVERSION RATE – Hz

CL = 0pF

CL = 30pF

CL = 50pF

Capacitive Loads on the Digital Outputs

Figure 12 shows the typical logic supply current vs. conversion

rate for various capacitive loads on the digital outputs.