AD671

REV. B

–12–

HIGH PERFORMANCE SAMPLE-AND-HOLD

AMPLIFIER (SHA)

In order to take full advantage of the AD671’s high speed capa-

bilities, a sample-and-hold amplifier (SHA) with fast acquisition

capabilities and rigid accuracy requirements is essential. One

possibility is a hybrid SHA such as the HTC-0300A, but often a

cost effective alternative like the one shown in Figure 13 may be

a better solution. This discrete SHA requires very few compo-

nents and is able to acquire signals to 0.01% accuracy in less

than 350 nanoseconds. Combined with the AD671, signals with

bandwidths up to 500 kHz can be converted with 12-bit accuracy.

SD5001

IN1

IN2

IN3

IN4

OUT1

OUT2

OUT3

OUT4

G1 G2 G3 G4

U8

AD841

U9

AD845

S/H

S/H

R6

R7

R8

250

R9

R10

10k

R11

250

U10

C24

C25

C26

C27

C28

20pF

C29

20pF

D1

1N4148

VR2 100k

R13

R14

226

C34

5pF

1k

10

11

4

6

5

15V

+

0.1

µF

2k

15V

–

0.1

µF

4

5

13

12

3

6

14

11

2

1

8

16

9

15V

–

1k

2

3

4

15V

–

7

1k

6

0.1

µF

0.1

µF

15V

+

IN

V

(5Vp–p)

ADJ

PEDESTAL

Figure 13. Discrete High Speed Sample-and-Hold Amplifier

CIRCUIT DESCRIPTION

The discrete SHA shown in Figure 13 is a closed-loop, nonin-

verting architecture which accepts 5 V p-p inputs. The overall

gain of the SHA is +2 in order to accommodate the 10 V input

span of the AD671. The AD841, with a 0.01% settling time of

110 ns, is the suggested input buffer to the SHA. The circuit

also employs a SD5001 which contains four ultrahigh speed

DMOS switches (Q1–Q4). The high CMRR, low input offset

current, and fast settling time of the AD845 op amp are all criti-

cal features necessary for optimal performance of the discrete

SHA.

In sample mode, Q1 and Q3 of the SD5001 are closed (Q2 and

Q4 are open). C28 is charged to the input voltage level at a rate

primarily determined by the time constant, R9 • C28. Simulta-

neously, C29 is connected to ground through a 250 ohm resis-

tor. If C28 is equal to C29, charge injection from Q1 will be

approximately equal to charge injection from Q3 based on the

symmetry of the circuit and the inherent matching of the switch

capacitances. The resultant pedestal errors appear as a common-

mode signal to the AD845. VR2, R13, R14, and C34 may be in-

cluded if further reduction of pedestal error is required.

In hold mode, Q2 and Q4 are closed (Q1 and Q3 are open) to

reduce feedthrough. The input signal is attenuated –78 dB

relative to the input signal at frequencies up to 500 kHz. The

AD845 buffers the voltage on C28 and also provides the wide-

band, low-impedance output necessary to drive the input of the

AD671.

Droop, which occurs as a result of leakage currents, will appear

on C28 and will similarly appear on C29. Like pedestal errors,

droop appears as a common-mode signal to the AD845 and is

greatly reduced by the differential nature of the circuit. Voltage

droop is typically 5

µV/µs.

CROSS COUPLED LATCH

As noted in the Theory of Operation, the ENCODE pulse is

specified to operate within a window of time. The circuit in Fig-

ure 14 can be used to generate a valid ENCODE pulse if a clock

pulse width of greater than 30 ns is available.

AD671

ENCODE

DAV

1/4

7402

1/4

7402

1/4

7402

Figure 14. Cross Coupled Latch

TIMING DESCRIPTION

Figure 15 shows the timing requirements for the discrete SHA.

The complementary S/H inputs are HCMOS-compatible al-

though larger gate voltages will improve performance by lower-

ing the on resistances of the DMOS switches. It should be noted

that a conversion is started before the SHA has settled to 0.01%

accuracy. The discrete SHA takes advantage of the fact that the

AD671 does not require a 12-bit accurate input until it is 150 ns

into its conversion cycle. See Figures 21, 22 and 23 for PCB

layout recommendations.

DAV

S/H

t

t

ACQUIRE

≈ 350ns

t

SETTLE

350ns

ENCODE

Figure 15. AD671 to Discrete SHA Timing Diagram

DYNAMIC PERFORMANCE

In most sampling applications the dynamic performance of the

system is limited by the performance of the SHA. The SHA’s

dynamic performance can be selected to meet the system sam-

pling requirements. Figures 16 and 17 are typical FFT plots

using the discrete SHA in Figure 13.

Figure 16. Typical FFT Plot of AD671 and Discrete SHA