AD723 datasheet(12/20 Pages) AD

12 / 20 page

REV. 0

AD723

–12–

Table I. Timing Description (See Figure 6)

Symbol

Name

Description

NTSC

PAL

tSW

Sync Width

Input valid sync width for burst

Min

2.8

µs

Min

3.3

µs

insertion (user-controlled).

Max

5.3

µs

Max

5.4

µs

tSB

Sync to Blanking

Minimum sync to color delay

End

(user-controlled).

Min

8.2

µs

Min

8.1

µs

tSM

Sync to Modulator

Delay to modulator clamp start.

8.4

µs

8.3

µs

Restore

tMW

Modulator Restore

Length of modulator offset clamp

1.1

µs

0.9

µs

Width

(no chroma during this period).

tSR

Sync to RGB DC

Delay to input clamping start.

5.4 ms

5.6 ms

Restore

tRW

DC Restore Width

Length of input clamp (no RGB

2.5

µs

2.3

µs

response during this period).

tSD

Sync to Delay Line

Delay to start of delay line

5.7

µs

5.8

µs

Reset

clock reset.

tDW

Delay Line Reset

Length of delay line clock reset

2.5

µs

2.3

µs

Width

(no luma response during this

period), also burst gate.

tSS

Sync Input to Luma

Delay from sync input assertion

Typ

310 ns

Typ

265 ns

Sync Output

to sync in LUMA output.

tBY

Blanking End to

Delay from RGB input assertion

Typ

340 ns

Typ

280 ns

LUMA Start

to LUMA output response.

tSC

Sync to Colorburst

Delay from valid horizontal sync

Typ

5.8

µs

Typ

5.9

µs

start to CRMA colorburst output.

tBC

Blanking End to

Delay from RGB input assertion

CRMA Start

to CRMA output response.

Typ

360 ns

Typ

300 ns

NOTES

1Input clock = 14.318180 MHz, STND pin = logic high.

2Input clock = 17.734475 MHz, STND pin = logic low.

tMW

tSW

tSB

tSR

tRW

tSD

tDW

tSS

tBY

tSC

tBC

HSYNC/VSYNC

(USER INPUTS)

RIN/GIN BIN

(USER INPUTS)

MODULATOR

RESTORE

INPUT

CLAMPS

BURST FLAG/

DELAY LINE RESET

tSM

Figure 6. Timing Diagram (Not to Scale)

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