SCL datasheet(19/29 Pages) EXAR

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Rev. 1.0.1

SUPERVISORY AND CONTROL

Power system design with XRP7724 is

accomplished using PowerArchitect™ design

tool version 5 (PA5). All figures referenced in

the following sections are taken from PA5.

Furthermore, the following sections reference

I2C commands. For more on these commands

please refer to ANP-38.

DIGITAL I/O

XRP7724 has two General Purpose Input

Output (GPIO) and three Power System Input

Output (PSIO) user configurable pins.

 GPIOs are 3.3V CMOS logic compatible

and 5V tolerant.

 PSIO configured as outputs are open

drain

and

require

external

pull-up

resistor. These I/Os are 3.3V and 5V

CMOS logic compatible, and up to 15V

capable.

The polarity of the GPIO/PSIO pins is set in

PA5 or with an I2C command.

Configuring GPIO/PSIOs

The following functions can be controlled from

or forwarded to any GPIO/PSIO:

 General Output – set with

an I2C

command

 General Input – triggers an interrupt;

state read with an I2C command

 Power

Group

Enable

–

controls

enabling and disabling of Group 1 and

Group 2

 Power Channel Enable – controls

enabling and disabling of a individual

channel including LDO3.3

 I2C Address Bit – controls an I2C

address bit

 Power OK – indicates that selected

channels have reached

their target

levels

and have not faulted. Multiple

channel selection is available in which

case the resulting signal is the AND logic

function of all channels selected

 ResetOut – is delayed Power OK. Delay

is programmable in 1msec increments

with the range of 0 to 255 msecs

 Low Vcc – indicates when Vcc has fallen

below the UVLO fault threshold and

when the UVLO condition clears (Vcc

voltage rises above the UVLO warning

level)

 Interrupt – the controller generated

interrupt selection and clearing is done

through I2C commands

Interrupt, Low Vcc, Power OK and ResetOut

signals can only be forwarded to a single

GPIO/PSIO.

In addition, the following are functions that

are unique to GPIO0 and GPIO1.

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