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SCL Datasheet(PDF) 24 Page - Exar Corporation |
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SCL Datasheet(HTML) 24 Page - Exar Corporation |
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24 / 29 page  X XR RP P7 77 72 24 4 Q Qu ua ad d C Ch ha an nn ne ell D Diig giitta all P PW WM M/ /P PF FM M P Prro og grra am mm ma ab blle e P Po ow we err M Ma an na ag ge em me en ntt S Sy ys stte em m © 2012 Exar Corporation 24/29 Rev. 1.0.1 be connected between the CPLL pin and AGND. In applications where this functionality is not desired, the CPLL capacitor is not necessary and can be omitted, and the pin shall be left floating. In addition, the user needs to make sure the function gets disabled through register settings. The external clock must be routed to GPIO0. The GPIO0 setting must reflect the range of the external clock applied to it: Sys_Clock/8 corresponds to the range of 10.9MHz to 14.7MHz while Sys_Clock/4 setting corresponds to the range of 21.8Mhz to 29.6MHz. The functionality is enabled in PowerArchitect™ 5.0 by selecting External Clock-in function under GPIO0. For more on details how to monitor PLL lock in-out, please contact Exar or your local Exar representative. CLOCK OUT XRP7724 can supply clock out to be used by another XRP7724 controller. The clock gets routed out through GPIO1 and can be set to system clock divided by 8 (Sys_Clock/8) or system clock divided by 4 (Sys_Clock/4) frequencies. The functionality is enabled in PA5 by selecting External Clock-Out function under GPIO1. CHANNEL CONTROL Channels including LDO3.3 can be controlled independently by any GPIO/PSIO or I2C command. Channels will start-up or shut- down following transitions of signals applied to GPIO/PSIOs set to control the channels. The control can always be overridden with an I2C command. Regardless whether the channels are controlled independently or are in a group, the ramp rates specified are followed (see the Power Sequencing section). Regulated voltages and voltage drops across synchronous FET on each switching channel can be read back using x I2C commands y. The regulated voltage read back resolution is 15mV, 30mV and 60mV per LSB depending on the target voltage range. The voltage drop across synchronous FET read back resolution is 1.25mV and 2.5mV per LSB depending on the range. Through an I2C command the host can check the status of the channels; whether they are in regulation or at fault. Regulated voltages can be dynamically changed on switching channels using I2C commands with resolution of 2.5mV, 5mV and 10mV depending on the target voltage range (in PWM mode only). For more information on I2C commands please contact Exar or your local Exar representative. POWER SEQUENCING All four channels and LDO3.3 can be grouped together and as such start-up and shut-down in a user defined sequence. Selecting none means channel(s) will not be assigned to any group and as such will be controlled independently. Group Selection There are three groups: |
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