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PIN FUNCTION DESCRIPTIONS

No.

Name

Function

AGND

Analog Ground.

2VOUTA

DAC A Voltage Output.

3VREF

DAC Reference voltage input terminal. Establishes DAC full-scale output voltage. Pin can be tied to VDD pin.

DGND

Digital Ground. Should be tied to analog GND.

Chip Select, active low input. Disables shift register loading when high. Does not effect

LDA or LDB operation.

CLK

Clock input, positive edge clocks data into shift register, MSB data bit first.

SDI

Serial Data Input, input data loads directly into the shift register.

LDA

Load DAC register strobe, level sensitive active low. Transfers shift register data to DAC A register. Asyn-

chronous active low input. See Control Logic Truth Table for operation.

Resets DAC register to zero condition or half-scale, depending on MSB pin logic level. Asynchronous active

low input.

LDB

Load DAC register strobe, level-sensitive active low. Transfers shift register data to DAC B register. Asyn-

chronous active low input. See Control Logic Truth Table for operation.

MSB

Digital Input: Logic High presets DAC registers to half-scale 800H (sets MSB bit to one) when the RS pin is

strobed; Logic Low clears all DAC registers to zero (000H) when the RS pin is strobed.

SHDN

Active low shutdown control input. Does not affect register contents as long as power is present on VDD. New

data can be loaded into the shift register and DAC register during shutdown. When device is powered up the

most recent data loaded into the DAC register will control the DAC output.

VDD

Positive power supply input. Specified range of operation +2.7 V to +5.5 V

VOUTB

DAC B Voltage Output.

PIN CONFIGURATIONS

TOP VIEW

(Not to Scale)

AGND

VOUTA

VREF

DGND

CLK

SDI

VOUTB

VDD

SHDN

MSB

LDB

LDA

AD7394

AD7395

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