PCA9538A datasheet(13/37 Pages) NXP

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PCA9538A

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Product data sheet

Rev. 1 — 28 September 2012

13 of 37

NXP Semiconductors

PCA9538A

Low-voltage 8-bit I2C-bus I/O port with interrupt and reset

8.3 Power-on reset requirements

In the event of a glitch or data corruption, PCA9538A can be reset to its default conditions

by using the power-on reset feature. Power-on reset requires that the device go through a

power cycle to be completely reset. This reset also happens when the device is

powered on for the first time in an application.

The two types of power-on reset are shown in Figure 15 and Figure 16.

Table 10 specifies the performance of the power-on reset feature for PCA9538A for both

types of power-on reset.

[1]

Level that VDD can glitch down to, but not cause a functional disruption when tw(gl)VDD <1 s.

[2]

Glitch width that will not cause a functional disruption when

V

DD(gl) =0.5  VDD.

Fig 15. VDD is lowered below 0.2 V or 0 V and then ramped up to VDD

Fig 16. VDD is lowered below the POR threshold, then ramped back up to VDD

002aah329

VDD

time

ramp-up

ramp-down

(dV/dt)r

(dV/dt)f

re-ramp-up

(dV/dt)r

time to re-ramp

when VDD drops

below 0.2 V or to VSS

td(rst)

002aah330

VDD

time

ramp-down

(dV/dt)f

ramp-up

(dV/dt)r

time to re-ramp

when VDD drops

to VPOR(min) − 50 mV

td(rst)

VI drops below POR levels

Table 10.

Recommended supply sequencing and ramp rates

Tamb =25 C (unless otherwise noted). Not tested; specified by design.

Symbol

Parameter

Condition

Min

Typ

Max

Unit

(dV/dt)f

fall rate of change of voltage

Figure 15

0.1

2000

(dV/dt)r

rise rate of change of voltage

Figure 15

0.1

2000

td(rst)

reset delay time

Figure 15; re-ramp time when

VDD drops to VSS

s

Figure 16; re-ramp time when

VDD drops to VPOR(min)  50 mV

s

V

DD(gl)

glitch supply voltage difference

Figure 17

[1] --

1.0

tw(gl)VDD

supply voltage glitch pulse width

Figure 17

[2] --

s

VPOR(trip)

power-on reset trip voltage

falling VDD

0.7

rising VDD

1.4

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