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PCAL9555APW Datasheet(PDF) 36 Page - NXP Semiconductors |
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PCAL9555APW Datasheet(HTML) 36 Page - NXP Semiconductors |
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36 / 46 page ![]() PCAL9555A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 — 3 October 2012 36 of 46 NXP Semiconductors PCAL9555A Low-voltage 16-bit GPIO with Agile I/O, interrupt and weak pull-up 15. Package outline Fig 32. Package outline SOT355-1 (TSSOP24) UNIT A1 A2 A3 bp cD(1) E(2) (1) eHE LLp QZ y w v θ REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 0.4 0.3 8 0 o o 0.13 0.1 0.2 1 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT355-1 MO-153 99-12-27 03-02-19 0.25 0.5 0.2 w M b p Z e 112 24 13 pin 1 index θ A A1 A2 L p Q detail X L (A ) 3 HE E c v M A X A D y 0 2.5 5 mm scale TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 A max. 1.1 |
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